Datasheet > LXT6234

LXT6234

更新时间： 2024-02-15 04:12:57

品牌	Logo	应用领域
英特尔 - INTEL		复用器
页数	文件大小	规格书
24页	287K
描述
E-Rate Multiplexer

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技术参数
数据手册

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LXT6234 技术参数

生命周期：	Transferred	零件包装代码：	QFP
包装说明：	QFP,	针数：	100
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.37	JESD-30 代码：	R-PQFP-G100
长度：	20 mm	功能数量：	1
端子数量：	100	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK	认证状态：	Not Qualified
座面最大高度：	3.4 mm	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	HDB3 ENCODER/DECODER	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	14 mm

LXT6234 数据手册

LXT6234

E-Rate Multiplexer

Datasheet

The LXT6234 E-Rate Multiplexer is a single-chip solution for multiplexing four tributary

channels into a single high speed data stream and for demultiplexing a high speed data stream

back to four tributary channels. All of the necessary circuitry is integrated into the LXT6234 E-

Rate Multiplexer; there is no need for an external framing device.

The LXT6234 E-Rate Multiplexer conforms to both the (ITU) G.742 and (ITU) G.751

multiplexing formats defined by the International Telecommunications Union (ITU; formerly

known as CCITT): G.742 recommendation for multiplexing four E1 channels into an E2 frame;

and the G.751 recommendation for multiplexing four E2 channels into an E3 frame.

The LXT6234 E-Rate Multiplexer also encodes and decodes HDB3 zero suppression line coding

used on E1, E2, and E3 signals. The coder and decoder input/output pins are externally

accessible, allowing either HDB3 or NRZ (non-return-to-zero) I/O to the multiplexer. The

LXT6234 E-Rate Multiplexer can also serve as a five channel HDB3 coder and decoder.

Applications

E1/E2 Multiplexer (2/8 Mbit/s)

E2/E3 Multiplexer (8/34 Mbit/s)

E1/E3 Multiplexer (2/34 Mbit/s)

Digital Loop Carrier (DLC) Terminal

Add / Drop Multiplexers (ADM)

4 - to - 1 Non-Standard Multiplexer

Product Features

Performs four-E1 to one-E2, or four-E2 to

one-E3 multiplexing. Five ICs will

implement a sixteen-E1 to one-E3

multiplexer.

Fully compliant with the G.742 and G.751

ITU recommendations. Fully compliant

with G.703 when used with LXT305/332

Line Interface.

A robust frame-acquisition and frame-

holding algorithm minimizes frame

slippage, acquires and holds frame below

10^-2bit error rate.

Four auxiliary low speed data or flag

channels are available via the Stuffing Bits

on each tributary channel.

Access to the Alarm bit and the National

bit. These can be used as recommended by

ITU or for proprietary use.

Five independent HDB3 CODECs allow

multiplexer I/O in either HDB3 or NRZ

formats. The LXT6234 can also function as

a stand alone five-channel HDB3

transcoder.

As of January 15, 2001, this document replaces the Level One document

LXT6234 E-Rate Multiplexer Datasheet.

Order Number: 249301-001

January 2001

12 3 4 5 6 7...24

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