PRELIMINARY
December 1993
LV8572A Low Voltage Real Time Clock (RTC)
General Description
l
The LV8572A is intended for use in microprocessor based
systems where information is required for multi-tasking, data
logging or general time of day/date information. This device
is implemented in low voltage silicon gate microCMOS tech-
nology to provide low standby power in battery back-up en-
vironments. The circuit’s architecture is such that it looks
like a contiguous block of memory or I/O ports. The address
space is organized as 2 software selectable pages of 32
bytes. This includes the Control Registers, the Clock Coun-
ters, the Alarm Compare RAM, and the Time Save RAM.
Any of the RAM locations that are not being used for their
intended purpose may be used as general purpose CMOS
RAM.
fails may be logged into RAM automatically when V
BB
. Additionally, two supply pins are provided. When
V
V
CC
l
V
CC
, internal circuitry will automatically switch from
the main supply to the battery supply. Status bits are provid-
ed to indicate initial application of battery power, system
BB
power, and low battery detect.
(Continued)
Features
Y
g
3.3V 10% supply
Y
Full function real time clock/calendar
Ð 12/24 hour mode timekeeping
Ð Day of week and day of years counters
Ð Four selectable oscillator frequencies
Ð Parallel resonant oscillator
Time and date are maintained from 1/100 of a second to
year and leap year in a BCD format, 12 or 24 hour modes.
Day of week, day of month and day of year counters are
provided. Time is controlled by an on-chip crystal oscillator
requiring only the addition of the crystal and two capacitors.
The choice of crystal frequency is program selectable.
Y
Power fail features
Ð Internal power supply switch to external battery
Ð Power Supply Bus glitch protection
Ð Automatic log of time into RAM at power failure
On-chip interrupt structure
Ð Periodic, alarm, and power fail interrupts
Up to 44 bytes of CMOS RAM
Y
Y
Power failure logic and control functions have been integrat-
ed on chip. This logic is used by the RTC to issue a power
fail interrupt, and lock out the mp interface. The time power
Block Diagram
TL/F/11417–1
FIGURE 1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/11417
RRD-B30M105/Printed in U. S. A.