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LTC2283UP

更新时间： 2024-11-07 05:43:43
品牌 Logo 应用领域
凌特 - Linear /
页数 文件大小 规格书
24页 576K
描述
Dual 12-Bit, 125Msps Low Power 3V ADC

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中文翻译

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LTC2283UP 数据手册

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LTC2283  
Dual 12-Bit, 125Msps  
Low Power 3V ADC  
FEATURES  
DESCRIPTION  
The LTC®2283 is a 12-bit 125Msps, low power dual 3V  
A/D converter designed for digitizing high frequency,  
wide dynamic range signals. The LTC2283 is perfect for  
demanding imaging and communications applications  
with AC performance that includes 70.1dB SNR and 82dB  
SFDR for signals at the Nyquist frequency.  
n
Integrated Dual 12-Bit ADCs  
n
Sample Rate: 125Msps  
n
Single 3V Supply (2.85V to 3.4V)  
n
Low Power: 790mW  
70.2dB SNR, 88dB SFDR  
n
n
110dB Channel ꢁsolation at 100MHz  
n
Flexible ꢁnput: 1V to 2V Range  
P-P  
P-P  
Typical DC specs include 0.ꢀLSB ꢁNL, 0.2LSB DNL. The  
transition noise is a low 0.32LSB  
n
n
n
n
n
6ꢀ0MHz Full Power Bandwidth S/H  
.
RMS  
Clock Duty Cycle Stabilizer  
A single 3V supply allows low power operation. A separate  
output supply allows the outputs to drive 0.5V to 3.6V  
logic.  
Shutdown and Nap Modes  
Data Ready Output Clock  
Pin Compatible Family  
125Msps: LTC2283 (12-Bit), LTC2285 (1ꢀ-Bit)  
105Msps: LTC2282 (12-Bit), LTC228ꢀ (1ꢀ-Bit)  
80Msps: LTC229ꢀ (12-Bit), LTC2299 (1ꢀ-Bit)  
65Msps: LTC2293 (12-Bit), LTC2298 (1ꢀ-Bit)  
ꢀ0Msps: LTC2292 (12-Bit), LTC2297 (1ꢀ-Bit)  
6ꢀ-Pin (9mm × 9mm) QFN Package  
A single-ended CLK input controls converter operation.  
An optional clock duty cycle stabilizer allows high perfor-  
mance at full speed for a wide range of clock duty cycles.  
A data ready output clock (CLKOUT) can be used to latch  
the output data.  
n
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other  
trademarks are the property of their respective owners.  
APPLICATIONS  
n
Wireless and Wired Broadband Communication  
n
ꢁmaging Systems  
n
Spectral Analysis  
Portable ꢁnstrumentation  
n
TYPICAL APPLICATION  
SNR vs Input Frequency,  
–1dB, 2V Range  
OV  
DD  
+
12-BꢁT  
PꢁPELꢁNED  
ADC CORE  
ꢁNPUT  
S/H  
ANALOG  
ꢁNPUT A  
73  
D11A  
OUTPUT  
DRꢁVERS  
•
•
•
72  
71  
–
D0A  
OGND  
70  
69  
68  
67  
66  
OF  
CLOCK/DUTY CYCLE  
CONTROL  
CLK A  
CLK B  
MUX  
CLOCK/DUTY CYCLE  
CONTROL  
CLKOUT  
OV  
DD  
65  
0
50  
100 150 200 250 300 350  
D11B  
+
2283 TA01b  
ꢁNPUT FREQUENCY (MHz)  
OUTPUT  
DRꢁVERS  
•
•
•
12-BꢁT  
PꢁPELꢁNED  
ADC CORE  
ANALOG  
ꢁNPUT B  
ꢁNPUT  
S/H  
D0B  
–
OGND  
2283 TA01  
2283fb  
1
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