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LTC2285CUP-TR PDF预览

LTC2285CUP-TR

更新时间: 2024-11-07 05:43:43
品牌 Logo 应用领域
凌特 - Linear /
页数 文件大小 规格书
24页 581K
描述
Dual 14-Bit, 125Msps Low Power 3V ADC

LTC2285CUP-TR 数据手册

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LTC2285  
Dual 14-Bit, 125Msps  
Low Power 3V ADC  
DESCRIPTION  
The LTC®2285 is a 14-bit 125Msps, low power dual 3V  
A/D converter designed for digitizing high frequency,  
wide dynamic range signals. The LTC2285 is perfect for  
demanding imaging and communications applications  
with AC performance that includes 72.2dB SNR and 82dB  
SFDR for signals at the Nyquist frequency.  
FEATURES  
n
Integrated Dual 14-Bit ADCs  
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Sample Rate: 125Msps  
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Single 3V Supply (2.85V to 3.4V)  
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Low Power: 790mW  
72.4dB SNR, 88dB SFDR  
n
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11ꢁdB Channel ꢀsolation at 1ꢁꢁMHz  
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Flexible ꢀnput: 1V to 2V Range  
P-P  
P-P  
Typical DC specs include 1.5LSB ꢀNL, ꢁ.0LSB DNL. The  
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n
n
n
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04ꢁMHz Full Power Bandwidth S/H  
transition noise is a low 1.3LSB  
.
RMS  
Clock Duty Cycle Stabilizer  
A single 3V supply allows low power operation. A separate  
output supply allows the outputs to drive ꢁ.5V to 3.0V  
logic.  
Shutdown and Nap Modes  
Data Ready Output Clock  
Pin Compatible Family  
125Msps: LTC2283 (12-Bit), LTC2285 (14-Bit)  
1ꢁ5Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)  
8ꢁMsps: LTC2294 (12-Bit), LTC2299 (14-Bit)  
05Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)  
4ꢁMsps: LTC2292 (12-Bit), LTC2297 (14-Bit)  
04-Pin (9mm × 9mm) QFN Package  
A single-ended CLK input controls converter operation.  
An optional clock duty cycle stabilizer allows high perfor-  
mance at full speed for a wide range of clock duty cycles.  
A data ready output clock (CLKOUT) can be used to latch  
the output data.  
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L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other  
trademarks are the property of their respective owners.  
APPLICATIONS  
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Wireless and Wired Broadband Communication  
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ꢀmaging Systems  
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Spectral Analysis  
Portable ꢀnstrumentation  
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TYPICAL APPLICATION  
SNR vs Input Frequency,  
OV  
–1dB, 2V Range  
DD  
+
14-BꢀT  
PꢀPELꢀNED  
ADC CORE  
ꢀNPUT  
S/H  
ANALOG  
ꢀNPUT A  
D13A  
75  
74  
73  
72  
71  
7ꢁ  
09  
08  
07  
00  
05  
OUTPUT  
DRꢀVERS  
DꢁA  
OGND  
OF  
CLOCK/DUTY CYCLE  
CONTROL  
CLK A  
CLK B  
MUX  
CLOCK/DUTY CYCLE  
CONTROL  
CLKOUT  
OV  
DD  
1ꢁꢁ 15ꢁ 2ꢁꢁ 25ꢁ 3ꢁꢁ 35ꢁ  
5ꢁ  
D13B  
+
OUTPUT  
DRꢀVERS  
2285 TAꢁ1b  
ꢀNPUT FREQUENCY (MHz)  
14-BꢀT  
PꢀPELꢀNED  
ADC CORE  
ANALOG  
ꢀNPUT B  
ꢀNPUT  
S/H  
DꢁB  
OGND  
2285 TAꢁ1  
2285fb  
1

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