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LTC2241IUP-12#TRPBF PDF预览

LTC2241IUP-12#TRPBF

更新时间: 2024-10-01 12:59:27
品牌 Logo 应用领域
凌特 - Linear 转换器
页数 文件大小 规格书
28页 598K
描述
LTC2241-12 - 12-Bit, 210Msps ADC; Package: QFN; Pins: 64; Temperature Range: -40°C to 85°C

LTC2241IUP-12#TRPBF 技术参数

是否Rohs认证:符合生命周期:Transferred
零件包装代码:QFN包装说明:HVQCCN, LCC64,.35SQ,20
针数:64Reach Compliance Code:compliant
ECCN代码:3A001.A.5.A.3HTS代码:8542.39.00.01
风险等级:5.09Is Samacsys:N
最大模拟输入电压:1 V最小模拟输入电压:-1 V
转换器类型:ADC, PROPRIETARY METHODJESD-30 代码:S-PQCC-N64
JESD-609代码:e3长度:9 mm
最大线性误差 (EL):0.0562%湿度敏感等级:1
模拟输入通道数量:1位数:12
功能数量:1端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
输出位码:OFFSET BINARY, 2'S COMPLEMENT BINARY输出格式:PARALLEL, WORD
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC64,.35SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:2.5 V认证状态:Not Qualified
采样速率:210 MHz采样并保持/跟踪并保持:SAMPLE
座面最大高度:0.8 mm子类别:Analog to Digital Converters
标称供电电压:2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:9 mm
Base Number Matches:1

LTC2241IUP-12#TRPBF 数据手册

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LTC2241-12  
12-Bit, 210Msps ADC  
U
FEATURES  
DESCRIPTIO  
The LTC®2241-12 is a 210Msps, sampling 12-bit A/D  
converter designed for digitizing high frequency, wide  
dynamic range signals. The LTC2241-12 is perfect for  
demanding communications applications with AC perfor-  
mancethatincludes65.5dBSNRand78dBSFDR.Ultralow  
jitter of 95fsRMS allows IF undersampling with excellent  
noise performance.  
Sample Rate: 210Msps  
65.5dB SNR  
78dB SFDR  
1.2GHz Full Power Bandwidth S/H  
Single 2.5V Supply  
Low Power Dissipation: 585mW  
LVDS, CMOS, or Demultiplexed CMOS Outputs  
Selectable Input Ranges: ±0.5V or ±1V  
DC specs include ±0.7LSB INL (typ), ±0.4LSB DNL (typ)  
and no missing codes over temperature.  
No Missing Codes  
Optional Clock Duty Cycle Stabilizer  
The digital outputs can be either differential LVDS, or  
single-ended CMOS. There are three format options for  
theCMOSoutputs:asinglebusrunningatthefulldatarate  
or two demultiplexed buses running at half data rate with  
either interleaved or simultaneous update. A separate  
output power supply allows the CMOS output swing to  
range from 0.5V to 2.625V.  
The ENC+ and ENCinputs may be driven differentially or  
singleendedwithasinewave, PECL, LVDS, TTL, orCMOS  
inputs. An optional clock duty cycle stabilizer allows high  
performance over a wide range of clock duty cycles.  
Shutdown and Nap Modes  
Data Ready Output Clock  
Pin Compatible Family  
250Msps: LTC2242-12 (12-Bit), LTC2242-10 (10-Bit)  
210Msps: LTC2241-12 (12-Bit), LTC2241-10 (10-Bit)  
170Msps: LTC2240-12 (12-Bit), LTC2240-10 (10-Bit)  
185Msps: LTC2220-1 (12-Bit)*  
170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)*  
135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)*  
64-Pin 9mm × 9Umm QFN Package  
APPLICATIO S  
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.  
All other trademarks are the property of their respective owners.  
*LTC2220-1, LTC2220, LTC2221, LTC2230, LTC2231 are 3.3V parts.  
Wireless and Wired Broadband Communication  
Cable Head-End Systems  
Power Amplifier Linearization  
Communications Test Equipment  
U
TYPICAL APPLICATIO  
2.5V  
SFDR vs Input Frequency  
V
DD  
0.5V  
TO 2.625V  
85  
80  
REFH  
REFL  
FLEXIBLE  
REFERENCE  
OV  
DD  
75  
70  
65  
60  
55  
50  
45  
40  
D11  
+
12-BIT  
PIPELINED  
ADC CORE  
CMOS  
OR  
CORRECTION  
LOGIC  
ANALOG  
INPUT  
OUTPUT  
DRIVERS  
INPUT  
S/H  
LVDS  
D0  
1V RANGE  
OGND  
2V RANGE  
CLOCK/DUTY  
CYCLE  
CONTROL  
0
100 200 300 400 500 600 700 800 9001000  
INPUT FREQUENCY (MHz)  
224112 G11  
224112 TA01  
ENCODE  
INPUT  
224112fa  
1

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