LTC2242-10
10-Bit, 250Msps ADC
FEATURES
DESCRIPTION
The LTC®2242-10 is a 250Msps, sampling 10-bit A/D con-
verterdesignedfordigitizinghighfrequency,widedynamic
range signals. The LTC2240-10 is perfect for demanding
communications applications with AC performance that
includes 60.5dB SNR and 78dB SFDR. Ultralow jitter of
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Sample Rate: 250Msps
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60.5dB SNR
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78dB SFDR
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1.2GHz Full Power Bandwidth S/H
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Single 2.5V Supply
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Low Power Dissipation: 740mW
95fs
allows IF undersampling with excellent noise
RMS
performance.
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LVDS, CMOS, or Demultiplexed CMOS Outputs
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Selectable Input Ranges: 0.5V or 1V
DC specs include 0.4LSB INL (typ), 0.2LSB DNL (typ)
and no missing codes over temperature.
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No Missing Codes
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Optional Clock Duty Cycle Stabilizer
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The digital outputs can be either differential LVDS, or
single-ended CMOS. There are three format options for
the CMOS outputs: a single bus running at the full data
rate or two demultiplexed buses running at half data rate
witheitherinterleavedorsimultaneousupdate. Aseparate
output power supply allows the CMOS output swing to
range from 0.5V to 2.625V.
Shutdown and Nap Modes
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Data Ready Output Clock
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Pin Compatible Family
250Msps: LTC2242-12 (12-Bit), LTC2242-10 (10-Bit)
210Msps: LTC2241-12 (12-Bit), LTC2241-10 (10-Bit)
170Msps: LTC2240-12 (12-Bit), LTC2240-10 (10-Bit)
185Msps: LTC2220-1 (12-Bit)*
170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)*
135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)*
+
–
The ENC and ENC inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance over a wide range of clock duty cycles.
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64-Pin 9mm × 9mm QFN Package
APPLICATIONS
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
*LTC2220-1, LTC2220, LTC2221, LTC2230, LTC2231 are 3.3V parts.
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Wireless and Wired Broadband Communication
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Cable Head-End Systems
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Power Amplifier Linearization
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Communications Test Equipment
TYPICAL APPLICATION
2.5V
SFDR vs Input Frequency
V
DD
85
80
75
70
65
60
55
50
45
40
0.5V
REFH
REFL
TO 2.625V
FLEXIBLE
REFERENCE
OV
DD
D9
•
•
•
D0
+
10-BIT
PIPELINED
ADC CORE
CMOS
OR
LVDS
CORRECTION
LOGIC
ANALOG
INPUT
OUTPUT
DRIVERS
INPUT
S/H
1V RANGE
–
2V RANGE
OGND
CLOCK/DUTY
CYCLE
CONTROL
0
100 200 300 400 500 600 700 800 9001000
INPUT FREQUENCY (MHz)
224210 G11
224210 TA01
ENCODE
INPUT
224210fc
1