Electrical Specifications Subject to Change
LTC2230/LTC2231
10-Bit,170Msps/
135Msps ADCs
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FEATURES
DESCRIPTIO
TheLTC®2230andLTC2231are170Msps/135Msps,sam-
pling 10-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. The LTC2230/
LTC2231 are perfect for demanding communications
applicationswithACperformancethatincludes61dBSNR
and 75dB spurious free dynamic range for signals
up to 200MHz. Ultralow jitter of 0.15psRMS allows
undersampling of IF frequencies with excellent noise
performance.
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Sample Rate: 170Msps/135 Msps
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61dB SNR up to 140MHz Input
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75dB SFDR up to 200MHz Input
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775MHz Full Power Bandwidth S/H
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Single 3.3V Supply
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Low Power Dissipation: 890mW/660mW
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LVDS, CMOS, or Demultiplexed CMOS Outputs
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Selectable Input Ranges: ±0.5V or ±1V
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No Missing Codes
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Optional Clock Duty Cycle Stabilizer
DC specs include ±0.2LSB INL (typ), ±0.1LSB DNL (typ)
■
Shutdown and Nap Modes
Data Ready Output Clock
and no missing codes over temperature. The transition
■
noise is a low 0.12LSBRMS
.
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Pin Compatible Family
The digital outputs can be either differential LVDS, or
single-ended CMOS. There are three format options for
theCMOSoutputs:asinglebusrunningatthefulldatarate
or two demultiplexed buses running at half data rate with
either interleaved or simultaneous update. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.3V.
The ENC+ and ENC– inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)
135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)
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64-Pin 9mm x 9mmQFN Package
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APPLICATIO S
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Wireless and Wired Broadband Communication
Cable Head-End Systems
Power Amplifier Linearization
Communications Test Equipment
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
3.3V
SFDR vs Input Frequency
V
DD
90
REFH
REFL
0.5V
FLEXIBLE
85
80
75
70
65
60
55
50
45
40
TO 3.3V
REFERENCE
4th OR HIGHER
OV
DD
D9
+
10-BIT
PIPELINED
ADC CORE
CMOS
OR
LVDS
•
•
•
2nd OR 3rd
CORRECTION
LOGIC
ANALOG
INPUT
OUTPUT
DRIVERS
INPUT
S/H
–
D0
OGND
CLOCK/DUTY
CYCLE
CONTROL
0
100
200
300
400
500
600
INPUT FREQUENCY (MHz)
22301 TA01
2230 TA01b
ENCODE INPUT
22301p
1