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LTC2233_15 PDF预览

LTC2233_15

更新时间: 2024-11-28 01:19:19
品牌 Logo 应用领域
凌特 - Linear /
页数 文件大小 规格书
28页 849K
描述
10-Bit,105Msps/ 80Msps ADCs

LTC2233_15 数据手册

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LTC2232/LTC2233  
10-Bit,105Msps/  
80Msps ADCs  
U
FEATURES  
DESCRIPTIO  
The LTC®2232 and LTC2233 are 105Msps/80Msps, sam-  
pling 10-bit A/D converters designed for digitizing high  
frequency, wide dynamic range signals. The LTC2232/  
LTC2233 are perfect for demanding communications  
applicationswithACperformancethatincludes61dBSNR  
and 75dB spurious free dynamic range for signals  
up to 200MHz. Ultralow jitter of 0.15psRMS allows  
undersampling of IF frequencies with excellent noise  
performance.  
Sample Rate: 105Msps/80Msps  
61dB SNR up to 140MHz Input  
75dB SFDR up to 200MHz Input  
775MHz Full Power Bandwidth S/H  
Single 3.3V Supply  
Low Power Dissipation: 475mW/366mW  
Selectable Input Ranges: ±0.5V or ±1V  
No Missing Codes  
Optional Clock Duty Cycle Stabilizer  
Shutdown and Nap Modes  
DC specs include ±0.15LSB INL (typ), ±0.1LSB DNL (typ)  
and ±0.8LSB INL, ±0.6LSB DNL over temperature. The  
Data Ready Output Clock  
Pin Compatible Family  
transition noise is a low 0.12LSBRMS  
.
135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)  
105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit)  
80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit)  
Aseparateoutputpowersupplyallowstheoutputstodrive  
0.5V to 3.6V logic.  
The ENC+ and ENCinputs may be driven differentially or  
singleendedwithasinewave, PECL, LVDS, TTL, orCMOS  
inputs. An optional clock duty cycle stabilizer allows high  
performance at full speed for a wide range of clock duty  
cycles.  
48-Pin 7mm x 7mm QFN Package  
U
APPLICATIO S  
Wireless and Wired Broadband Communication  
Cable Head-End Systems  
Power Amplifier Linearization  
Communications Test Equipment  
, LTC and LT are registered trademarks of Linear Technology Corporation.  
All other trademarks are the property of their respective owners.  
U
TYPICAL APPLICATIO  
3.3V  
V
SFDR vs Input Frequency  
DD  
0.5V  
90  
TO 3.6V  
REFH  
FLEXIBLE  
REFERENCE  
85  
REFL  
4th OR HIGHER  
OV  
DD  
80  
75  
70  
65  
60  
55  
50  
D9  
+
10-BIT  
PIPELINED  
ADC CORE  
CORRECTION  
LOGIC  
ANALOG  
INPUT  
OUTPUT  
DRIVERS  
INPUT  
S/H  
2nd OR 3rd  
D0  
OGND  
CLOCK/DUTY  
CYCLE  
CONTROL  
0
200  
300  
400  
500  
600  
100  
22323 TA01b  
INPUT FREQUENCY (MHz)  
22323 TA01  
ENCODE INPUT  
22323fa  
1

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