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LTC2231CUP PDF预览

LTC2231CUP

更新时间: 2024-11-26 22:35:23
品牌 Logo 应用领域
凌特 - Linear /
页数 文件大小 规格书
28页 695K
描述
Electrical Specifications Subject to Change

LTC2231CUP 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:QFN包装说明:HVQCCN, LCC64,.35SQ,20
针数:64Reach Compliance Code:not_compliant
ECCN代码:3A991.C.1HTS代码:8542.39.00.01
风险等级:5.08最大模拟输入电压:1 V
最小模拟输入电压:-1 V转换器类型:ADC, PROPRIETARY METHOD
JESD-30 代码:S-PQCC-N64JESD-609代码:e0
长度:9 mm最大线性误差 (EL):0.0781%
湿度敏感等级:1模拟输入通道数量:1
位数:10功能数量:1
端子数量:64最高工作温度:70 °C
最低工作温度:输出位码:OFFSET BINARY, 2'S COMPLEMENT BINARY
输出格式:PARALLEL, WORD封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装等效代码:LCC64,.35SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):235电源:3.3 V
认证状态:Not Qualified采样速率:135 MHz
采样并保持/跟踪并保持:SAMPLE座面最大高度:0.8 mm
子类别:Analog to Digital Converters标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:9 mmBase Number Matches:1

LTC2231CUP 数据手册

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Electrical Specifications Subject to Change  
LTC2230/LTC2231  
10-Bit,170Msps/  
135Msps ADCs  
U
FEATURES  
DESCRIPTIO  
TheLTC®2230andLTC2231are170Msps/135Msps,sam-  
pling 10-bit A/D converters designed for digitizing high  
frequency, wide dynamic range signals. The LTC2230/  
LTC2231 are perfect for demanding communications  
applicationswithACperformancethatincludes61dBSNR  
and 75dB spurious free dynamic range for signals  
up to 200MHz. Ultralow jitter of 0.15psRMS allows  
undersampling of IF frequencies with excellent noise  
performance.  
Sample Rate: 170Msps/135 Msps  
61dB SNR up to 140MHz Input  
75dB SFDR up to 200MHz Input  
775MHz Full Power Bandwidth S/H  
Single 3.3V Supply  
Low Power Dissipation: 890mW/660mW  
LVDS, CMOS, or Demultiplexed CMOS Outputs  
Selectable Input Ranges: ±0.5V or ±1V  
No Missing Codes  
Optional Clock Duty Cycle Stabilizer  
DC specs include ±0.2LSB INL (typ), ±0.1LSB DNL (typ)  
Shutdown and Nap Modes  
Data Ready Output Clock  
and no missing codes over temperature. The transition  
noise is a low 0.12LSBRMS  
.
Pin Compatible Family  
The digital outputs can be either differential LVDS, or  
single-ended CMOS. There are three format options for  
theCMOSoutputs:asinglebusrunningatthefulldatarate  
or two demultiplexed buses running at half data rate with  
either interleaved or simultaneous update. A separate  
output power supply allows the CMOS output swing to  
range from 0.5V to 3.3V.  
The ENC+ and ENCinputs may be driven differentially or  
single ended with a sine wave, PECL, LVDS, TTL, or CMOS  
inputs. An optional clock duty cycle stabilizer allows high  
performance at full speed for a wide range of clock duty  
cycles.  
170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)  
135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)  
64-Pin 9mm x 9mmQFN Package  
U
APPLICATIO S  
Wireless and Wired Broadband Communication  
Cable Head-End Systems  
Power Amplifier Linearization  
Communications Test Equipment  
, LTC and LT are registered trademarks of Linear Technology Corporation.  
U
TYPICAL APPLICATIO  
3.3V  
SFDR vs Input Frequency  
V
DD  
90  
REFH  
REFL  
0.5V  
FLEXIBLE  
85  
80  
75  
70  
65  
60  
55  
50  
45  
40  
TO 3.3V  
REFERENCE  
4th OR HIGHER  
OV  
DD  
D9  
+
10-BIT  
PIPELINED  
ADC CORE  
CMOS  
OR  
LVDS  
2nd OR 3rd  
CORRECTION  
LOGIC  
ANALOG  
INPUT  
OUTPUT  
DRIVERS  
INPUT  
S/H  
D0  
OGND  
CLOCK/DUTY  
CYCLE  
CONTROL  
0
100  
200  
300  
400  
500  
600  
INPUT FREQUENCY (MHz)  
22301 TA01  
2230 TA01b  
ENCODE INPUT  
22301p  
1

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