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LTC2217 PDF预览

LTC2217

更新时间: 2024-11-29 14:58:03
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
32页 1273K
描述
16位、105Msps低噪声ADC

LTC2217 数据手册

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LTC2217  
16-Bit, 105Msps  
Low Noise ADC  
FEATURES  
DESCRIPTION  
Sample Rate: 105Msps  
TheLTC®2217isa105Mspssampling16-bitA/Dconverter  
designedfordigitizinghighfrequency,widedynamicrange  
signals with input frequencies up to 400MHz. The input  
81.3dBFS Noise Floor  
100dB SFDR  
SFDR >90dB at 70MHz  
range of the ADC is fixed at 2.75V  
.
P-P  
85fs  
Jitter  
RMS  
The LTC2217 is perfect for demanding communications  
applications,withACperformancethatincludes81.3dBFS  
Noise Floor and 100dB spurious free dynamic range  
2.75V Input Range  
P-P  
400MHz Full Power Bandwidth S/H  
Optional Internal Dither  
(SFDR). Ultra low jitter of 85fs  
allows undersampling  
RMS  
Optional Data Output Randomizer  
LVDS or CMOS Outputs  
ofhighinputfrequencieswhilemaintainingexcellentnoise  
performance.MaximumDCspecificationsinclude 3.5LSB  
INL, 1LSB DNL (no missing codes).  
Single 3.3V Supply  
Power Dissipation: 1.19W  
Clock Duty Cycle Stabilizer  
Pin Compatible with LTC2208  
64-Pin (9mm × 9mm) QFN Package  
The digital output can be either differential LVDS or  
single-ended CMOS. There are two format options for the  
CMOS outputs: a single bus running at the full data rate or  
demultiplexed buses running at half data rate. A separate  
output power supply allows the CMOS output swing to  
range from 0.5V to 3.6V.  
APPLICATIONS  
Telecommunications  
+
The ENC and ENC inputs may be driven differentially  
or single-ended with a sine wave, PECL, LVDS, TTL or  
CMOS inputs. An optional clock duty cycle stabilizer al-  
lows high performance at full speed with a wide range of  
clock duty cycles.  
Receivers  
Cellular Base Stations  
Spectrum Analysis  
Imaging Systems  
ATE  
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.  
All other trademarks are the property of their respective owners. Patents Pending.  
TYPICAL APPLICATION  
3.3V  
SENSE  
64k Point FFT,  
FIN = 4.9MHz, –1dBFS  
OV  
DD  
1.575V  
COMMON MODE  
BIAS VOLTAGE  
INTERNAL ADC  
REFERENCE  
GENERATOR  
V
0.5V TO 3.6V  
1μF  
CM  
0
–10  
2.2μF  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
OF  
CLKOUT  
D15  
+
AIN  
+
16-BIT  
PIPELINED  
ADC CORE  
OUTPUT  
DRIVERS  
CORRECTION  
LOGIC AND  
SHIFT REGISTER  
CMOS  
OR  
LVDS  
ANALOG  
INPUT  
S/H  
AMP  
AIN  
D0  
–90  
OGND  
–100  
–110  
–120  
–130  
CLOCK/DUTY  
CYCLE  
CONTROL  
3.3V  
1μF  
V
DD  
1μF  
1μF  
GND  
2217 TA01  
0
10  
20  
30  
40  
50  
FREQUENCY (MHz)  
+
ENC  
ENC  
SHDN DITH MODE LVDS RAND  
ADC CONTROL INPUTS  
2217 TA01b  
2217f  
1

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