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LTC2217IUP#TR PDF预览

LTC2217IUP#TR

更新时间： 2024-11-26 12:58:35
品牌 Logo 应用领域
凌特 - Linear /
页数 文件大小 规格书
28页 893K
描述
IC 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64, 9 X 9 MM, PLASTIC, MO-220WNJR, QFN-64, Analog to Digital Converter

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LTC2217IUP#TR 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Transferred零件包装代码：QFN
包装说明：HVQCCN, LCC64,.35SQ,20针数：64
Reach Compliance Code：not_compliantECCN代码：3A001.A.5.A.5
HTS代码：8542.39.00.01风险等级：5.1
Is Samacsys：N最大模拟输入电压：2.75 V
最小模拟输入电压：转换器类型：ADC, PROPRIETARY METHOD
JESD-30 代码：S-PQCC-N64JESD-609代码：e0
长度：9 mm最大线性误差 (EL)：0.0053%
湿度敏感等级：1模拟输入通道数量：1
位数：16功能数量：1
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C输出位码：OFFSET BINARY, 2'S COMPLEMENT BINARY
输出格式：PARALLEL, WORD封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装等效代码：LCC64,.35SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：235电源：3.3 V
认证状态：Not Qualified采样速率：105 MHz
采样并保持/跟踪并保持：SAMPLE座面最大高度：0.8 mm
子类别：Analog to Digital Converters标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：20
宽度：9 mmBase Number Matches：1

LTC2217IUP#TR 数据手册

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LTC2195  
LTC2194/LTC2193  
16-Bit, 125/105/80Msps  
Low Power Dual ADCs  
FEATURES  
DESCRIPTION  
The LTC®2195/LTC2194/LTC2193 are 2-channel, simul-  
taneous sampling 16-bit A/D converters designed for  
digitizing high frequency, wide dynamic range signals.  
They are perfect for demanding communications applica-  
tions with AC performance that includes 76.8dB SNR and  
90dB spurious free dynamic range (SFDR). Ultralow jitter  
n
2-Channel Simultaneous Sampling ADC  
n
Serial LVDS Outputs: 1, 2 or 4 Bits per Channel  
n
76.8dB SNR  
90dB SFDR  
n
n
Low Power: 432mW/360mW/249mW Total  
n
216mW/180mW/125mW per Channel  
n
Single 1.8V Supply  
of0.07ps  
allowsundersamplingofIFfrequencieswith  
RMS  
n
Selectable Input Ranges: 1V to 2V  
excellent noise performance.  
P-P  
P-P  
n
n
n
n
550MHz Full-Power Bandwidth S/H  
DC specs include 2LSB INL (typ), 0.5LSB DNL (typ)  
and no missing codes over temperature. The transition  
Shutdown and Nap Modes  
Serial SPI Port for Configuration  
52-Pin (7mm × 8mm) QFN Package  
noise is 3.4LSB  
.
RMS  
To minimize the number of data lines the digital outputs  
are serial LVDS. Each channel outputs two bits or four bits  
at a time. At lower sampling rates there is a one bit per  
channel option. The LVDS drivers have optional internal  
termination and adjustable output levels to ensure clean  
signal integrity.  
APPLICATIONS  
n
Communications  
n
Cellular Base Stations  
n
Software-Defined Radios  
Portable Medical Imaging  
Multi-Channel Data Acquisition  
n
+
–
The ENC and ENC inputs may be driven differentially or  
single ended with a sine wave, PECL, LVDS, TTL or CMOS  
inputs. An internal clock duty cycle stabilizer allows high  
performance at full speed for a wide range of clock duty  
cycles.  
n
n
Nondestructive Testing  
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear  
Technology Corporation. All other trademarks are the property of their respective owners.  
TYPICAL APPLICATION  
2-Tone FFT, fIN = 70MHz and 69MHz  
1.8V  
1.8V  
OV  
0
–10  
–20  
–30  
–40  
–50  
V
DD  
DD  
OUT1A  
OUT1B  
OUT1C  
OUT1D  
OUT2A  
OUT2B  
OUT2C  
OUT2D  
CH1  
ANALOG  
INPUT  
16-BIT  
ADC CORE  
S/H  
S/H  
CH2  
ANALOG  
INPUT  
SERIALIZED  
16-BIT  
ADC CORE  
DATA  
SERIALIZER  
–60  
LVDS  
–70  
OUTPUTS  
–80  
–90  
–100  
–110  
–120  
ENCODE  
INPUT  
PLL  
DATA CLOCK OUT  
FRAME  
GND  
OGND  
0
20  
30  
40  
50  
60  
10  
219543 TA01a  
FREQUENCY (MHz)  
219543 TA01b  
219543f  
1
1234567...28

中文翻译

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