Datasheet > LTC2220

LTC2220

更新时间： 2023-12-20 18:46:00

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
32页	797K
描述
12 位、170Msps ADC

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数据手册

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LTC2220 数据手册

LTC2220/LTC2221

12-Bit,170Msps/

135Msps ADCs

FEATURES

DESCRIPTIO

TheLTC^®2220andLTC2221are170Msps/135Msps,sam-

pling 12-bit A/D converters designed for digitizing high

frequency, wide dynamic range signals. The LTC2220/

LTC2221 are perfect for demanding communications

applications with AC performance that includes 67.5dB

SNR and 80dB spurious free dynamic range for signals

up to 170MHz. Ultralow jitter of 0.15ps_RMSallows

undersampling of IF frequencies with excellent noise

performance.

■

Sample Rate: 170Msps/135Msps

■

67.5dB SNR up to 140MHz Input

■

80dB SFDR up to 170MHz Input

■

775MHz Full Power Bandwidth S/H

■

Single 3.3V Supply

■

Low Power Dissipation: 890mW/660mW

■

LVDS, CMOS, or Demultiplexed CMOS Outputs

■

Selectable Input Ranges: ±0.5V or ±1V

■

No Missing Codes

■

Optional Clock Duty Cycle Stabilizer

DC specs include ±0.4LSB INL (typ), ±0.3LSB DNL (typ)

■

Shutdown and Nap Modes

and no missing codes over temperature. The transition

■

Data Ready Output Clock

noise is a low 0.5LSB_RMS

■

Pin Compatible Family

The digital outputs can be either differential LVDS, or

single-ended CMOS. There are three format options for

theCMOSoutputs:asinglebusrunningatthefulldatarate

or two demultiplexed buses running at half data rate with

either interleaved or simultaneous update. A separate

output power supply allows the CMOS output swing to

range from 0.5V to 3.6V.

The ENC⁺and ENC^–inputs may be driven differentially or

singleendedwithasinewave, PECL, LVDS, TTL, orCMOS

inputs. An optional clock duty cycle stabilizer allows high

performance at full speed for a wide range of clock duty

cycles.

185Msps: LTC2220-1 (12-Bit)

170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)

135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)

64-Pin 9mm × 9mm QFN Package

■

APPLICATIO S

■

Wireless and Wired Broadband Communication

■

Cable Head-End Systems

■

Power Amplifier Linearization

Communications Test Equipment

■

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

TYPICAL APPLICATIO

SFDR vs Input Frequency

3.3V

100

0.5V

TO 3.6V

REFH

REFL

FLEXIBLE

REFERENCE

4th OR HIGHER

D11

12-BIT

PIPELINED

ADC CORE

CMOS

•

CORRECTION

LOGIC

ANALOG

INPUT

OUTPUT

DRIVERS

INPUT

S/H

LVDS

–

2nd OR 3rd

OGND

CLOCK/DUTY

CYCLE

CONTROL

22201 TA01

200

300

100

400

500

600

ENCODE

INPUT

INPUT FREQUENCY (MHz)

22201 TA01b

22201fa

12 3 4 5 6 7...32

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