Datasheet > LS7082N1

LS7082N1

更新时间： 2024-11-24 12:20:07

品牌	Logo	应用领域
LSI		转换器时钟
页数	文件大小	规格书
4页	362K
描述
QUADRATURE CLOCK CONVERTER

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数据手册

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LS7082N1 数据手册

LS7082N1

LSI/CSI

_®L

LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405

A3800

April 2009

QUADRATURE CLOCK CONVERTER

PIN ASSIGNMENT - TOP VIEW

FEATURES:

• x1, x2 and x4 mode selection

• Up to 16MHz output clock frequency

• INDEX input and output

• UP/DOWN indicator output

• Programmable output clock pulse width

• On-chip filtering of inputs for optical or

magnetic encoder applications.

• TTL and CMOS compatible I/Os

• +3V to +12V operation (VDD - VSS)

• LS7082N1 (DIP); LS7082N1-S (SOIC ) - See Figure 1

DD (+V )

INDX

UPCK

DNCK

UP/DN

INDX

RBIAS

SS (-V )

DESCRIPTION:

x4/x1

The LS7082N1 is a CMOS quadrature clock converter. Quad-

rature clocks derived from optical or magnetic encoders, when

applied to the A and B Inputs of the LS7082N1, are converted

to strings of Up Clocks and Down Clocks. Pulses derived from

the Index Track of an encoder, when applied to the INDX input,

produce absolute position reference pulses which are syn-

chronized to the Up Clocks and Down Clocks. These outputs

can be interfaced directly with standard Up/Down counters for

FIGURE 1

TABLE 1. MODE SELECTION TRUTH TABLE

direction and position sensing of the encoder.

x2 Input

x4/x1 Input

MODE

0 or 1

INPUT/OUTPUT DESCRIPTION:

VDD (Pin 1)

Supply Voltage positive terminal.

x4/x1 (Pin 10)

INDX (Pin 2)

This input selects between x1 and x4 modes of operation.

See Table 1 for Mode Selection Truth Table and Figure 2 for

Input/Output timing relationship.

Encoder Index pulses are applied to this input.

RBIAS (Pin 3)

Input for external component connection. A resistor con-

nected between this input and VSS adjusts the output clock

pulse width (Tow). For proper operation, the output clock

pulse width must be less than or equal to the A, B pulse

separation (TOW £ TPS).

UP/DN (Pin 11)

The count direction at any instant is indicated at this output.

An UP count direction is indicated by a high, and a DOWN

count direction is indicated by a low (See Figure 2).

DNCK (Pin 12)

VSS (Pin 4)

This DOWN Clock output consists of low-going pulses gen-

erated when A input lags the B input (See Figure 2).

Supply Voltage negative terminal.

A (Pin 5)

UPCK (Pin 13)

Quadrature Clock Input A. This input has a filter circuit to

validate input logic level and eliminate encoder dither.

This UP Clock output consists of low-going pulses gener-

ated when A input leads the B input (See Figure 2).

x2 (Pin 8)

INDX (Pin 14)

A low level applied to this input selects x2 mode of opera-

tion. See Table 1 for Mode Selection Truth Table and

Figure 2 for Input/Output timing relationship.

This output consists of low-going pulses generated by a

positive clock transition at the A input when INDX input

is high and B input is low and a negative clock transition

at the B input when INDX input is high and A input is high.

(See Figure 2).

B (Pin 9)

Quadrature Clock Input B. This input has a filter circuit

identical to input A.

NOTE: All unused input pins must be tied to VDD or VSS.

7082N1-043009-1

12 3 4

中文翻译

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与LS7082N1相关器件

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