Datasheet > LS7083NS-14

LS7083NS-14

更新时间： 2024-11-27 12:48:15

品牌	Logo	应用领域
LSI		转换器时钟
页数	文件大小	规格书
4页	186K
描述
QUADRATURE CLOCK CONVERTER

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数据手册

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LS7083NS-14 数据手册

LS7083NS‐14

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June 2013

QUADRATURE CLOCK CONVERTER

FEATURES:

•

X1 and x4 mode selection

Up to 16MHz output clock frequency

PIN ASSIGNMENT

Programmable output clock pulse width

On-chip filtering of inputs for optical or magnetic encoder applications

TTL and CMOS compatible I/Os

TOP VIEW

+3V to +12V operation (V_DD– V_SS)

LS7083NS-14 (SOIC) – See Figure 1.

Applications:

Interface incremental encoders to Up/Down Counters

(See Figure 6A and 6B)

•

DESCRIPTION:

The LS7083NS-14 is a CMOS quadrature clock converter. Quadrature clocks derived

from optical or magnetic encoders, when applied to the A and B inputs of the

LS7083NS-14 are converted to strings of Up Clocks and Down Clocks. These outputs

can be interfaced directly with standard Up/Down counters for direction and position

sensing of the encoder.

INPUT/OUTPUT DESCRIPTION:

V_DD(Pin 2)

Supply voltage positive terminal.

RBIAS (Pin 3)

Input for external component connection. A resistor connected between this input and

FIGURE 1.

V_SSadjusts the output clock pulse width (T_OW). For proper operation, the output clock

pulse width must be less than or equal to the A, B pulse separation (T_OW≤ T_PS).

_SS(Pin 4)

DNCK (Pin 12)

Supply voltage negative terminal.

This is the DOWN Clock Output. This output

consists of low-going pulses generated when A

input lags the B input.

A (Pin 5)

Quadrature Clock Input A. This input has a filter circuit to validate input logic level and

eliminate encoder dither.

UPCK (Pin 13)

This is the UP Clock Output. This output consists of

low-going pulses generated when A input leads the

B input.

B (Pin 10)

Quadrature Clock Input B. This input has a filter circuit identical to input A.

Mode (Pin 11)

Mode is a 3-state input to select resolutions x1, x2, or x4. The selected resolution

multiplies the input quadrature clock rate by 1, 2 and 4 respectively; in producing the

outputs UPCK/DNCK and CLK (see Figure 2).

The Mode input logic levels selects resolutions as follows:

Logic 0 = x1 Float = x2 Logic 1 = x4

7083NS-14-062713-1

12 3 4

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