Datasheet > LS4118

LS4118

更新时间： 2024-11-15 22:31:03

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Linear Systems		输入元件
页数	文件大小	规格书
1页	15K
描述
ULTRA-HIGH INPUT IMPEDANCE N-CHANNEL JFET

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LS4118 数据手册

LS4117, 4118, 4119

ULTRA-HIGH INPUT IMPEDANCE

N-CHANNEL JFET

Linear Integrated Systems

FEATURES

LOW POWER

I_DSS<90 µA (2N4117)

I_GSS<1 pA (2N4117A Series)

MINIMUM CIRCUIT LOADING

Case

ABSOLUTE MAXIMUM RATINGS (NOTE 1)

@ 25°C (unless otherwise noted)

Gate-Source or Gate-Drain Voltage (NOTE 1) -40V

Gate-Current

Total Device Dissipation

(Derate 2mW/°C to 175°C)

Storage Temperature Range

Lead Temperature

50mA

300mW

-65°C to +175°C

TO-72

Bottom View

(1/16" from case for 10 seconds)

255°C

ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)

2N4117/A

2N4118

2N4119

FN4117/A

2N4118A

2N4119A

SYMBOL

CHARACTERISTICS

Gate Reverse Current

Standard only

MIN MAX MIN

MAX MIN MAX UNITS

CONDITIONS

I_GSS

-10

-25

-1

-10

-25

-1

-10

-25

-1

V_GS= -20V V_DS= 0

150°C

I_GSS

Gate Reverse Current

V_GS=-20V V_DS= 0

"A" Series only

-2.5

BV_GSS

Gate-Source Breakdown Voltage -40

-40

I_G=-1µA

V_DS= 0

V_GS(off)Gate-Source Cutoff Voltage

I_DSSSaturation Drain Current

(NOTE 2)

Common-Source Forward

-0.6

-1.8

-1

-3

-2

-6

V_DS=10V I_D= 1nA

V_DS=10V V_GS= 0

0.03

0.09 0.08

0.24

0.20 0.60

FN4117/A 0.015

g_fs

210

250

100

330

Transconductance

Common-Source Output

Conductance

(NOTE 2)

f=1kHz

µmho

g_os

C_iss

C_rss

Common-Source Input

Capacitance

V_DS= 10V V_GS= 0

f=1MHz

Common-Source Reverse

Transfer Capacitance

1.5

NOTES:

1. Due to symmetrical geometry, these units may be operated with source and drain leads interchanged.

2. This parameter is measured during a 2 ms interval 100 ms after power is applied. (Not a JEDEC condition.)

Linear Integrated Systems 4042 Clipper Ct., Fremont, CA 94538 TEL: (510) 490-9160 • FAX: (510) 353-0261

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