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LS4119(TO-71)

更新时间: 2024-11-16 19:43:35
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Transistor

LS4119(TO-71) 数据手册

  
LS4119  
N-CHANNEL JFET  
Linear Systems replaces discontinued Siliconix 2N4119  
The LS4119 is an Ultra-High Input Impedance N-Channel JFET  
FEATURES  
The LS4119 provides ultra-high input impedance. The  
device is specified with a 10-pA limit and is ideal for use  
as a high-impedance sensitive front-end amplifier.  
DIRECT REPLACEMENT FOR SILICONIX 2N4119  
LOW POWER  
IDSS<90 µA  
IGSS<10 pA  
MINIMUM CIRCUIT LOADING  
ABSOLUTE MAXIMUM RATINGS  
@ 25°C (unless otherwise noted)  
LS4119 Benefits:  
ƒ
Insignificant Signal Loss/Error Voltage  
with High-Impedance Source  
Maximum Temperatures  
Storage Temperature  
Operating Junction Temperature  
Maximum Power Dissipation  
Continuous Power Dissipation  
MAXIMUM CURRENT  
Gate Current (Note 1)  
MAXIMUM VOLTAGES  
Gate to Drain or Gate to Source (Note 2)  
ƒ
ƒ
ƒ
Low Power Consumption (Battery)  
Maximum Signal Output, Low Noise  
High Sensitivity to Low-Level Signals  
65°C to +175°C  
55°C to +150°C  
LS4119 Applications:  
300mW  
50mA  
40V  
ƒ
ƒ
ƒ
ƒ
High-Impedance Transducer  
Smoke Detector Input  
Infrared Detector Amplifier  
Precision Test Equipment  
LS4119 ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)  
SYMBOL  
BVGSS  
VGS(off)  
IDSS  
CHARACTERISTIC  
MIN  
40  
2  
0.20  
‐‐  
‐‐  
100  
‐‐  
TYP.  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
MAX  
‐‐  
6  
0.60  
10  
25  
330  
10  
UNITS  
V
V
mA  
pA  
CONDITIONS  
Gate to Source Breakdown Voltage  
Gate to Source Cutoff Voltage  
Gate to Source Saturation Current  
Gate Leakage Current  
IG = 1µA, VDS = 0V  
VDS = 10V, ID = 1nA  
VDS = 10V, VGS = 0V  
VGS = 20V, VDS = 0V  
IGSS  
Click To Buy  
VGS = 20V, VDS = 0V, 150°C  
VDS = 10V, VGS = 0V, f = 1kHz  
gfs  
gos  
Ciss  
Crss  
Forward Transconductance(Note 3)  
Output Conductance  
µmho  
pF  
Input Capacitance  
‐‐  
‐‐  
3
1.5  
VDS = 10V, VGS = 0V, f = 1MHz  
Reverse Transfer Capacitance  
1 . Absolute maximum ratings are limiting values above which LS4119 serviceability may be impaired.  
2. Due to symmetrical geometry, these units may be operated with source and drain leads interchanged  
3. This parameter is measured during a 2ms interval 100ms after power is applied. (Not a JEDEC condition.)  
NOTES  
Micross Components Europe  
Available Packages:  
TO-71 (Bottom View)  
LS4119 in TO-71  
LS4119 in bare die.  
Please contact Micross for full  
package and die dimensions  
Tel: +44 1603 788967  
Email: chipcomponents@micross.com  
Web: http://www.micross.com/distribution  
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed  
for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Linear Integrated Systems.  
Micross Components Ltd, United Kingdom, Tel: +44 1603 788967, Fax: +44 1603788920, Email: chipcomponents@micross.com Web: www.micross.com/distribution.aspx  

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