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LPTM10-1247-3TG128C PDF预览

LPTM10-1247-3TG128C

更新时间： 2024-10-22 19:52:47
品牌 Logo 应用领域
莱迪思 - LATTICE 光电二极管
页数 文件大小 规格书
81页 6496K
描述
Analog Circuit, 1 Func, PQFP128, HALOGEN FREE AND ROHS COMPLIANT, TQFP-128

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LPTM10-1247-3TG128C 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：QFP包装说明：HALOGEN FREE AND ROHS COMPLIANT, TQFP-128
针数：128Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：2.11模拟集成电路 - 其他类型：ANALOG CIRCUIT
JESD-30 代码：S-PQFP-G128长度：14 mm
功能数量：1端子数量：128
最高工作温度：85 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP128,.64SQ,16封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5/5,3/3.6 V认证状态：Not Qualified
座面最大高度：1.6 mm子类别：Power Management Circuits
最大供电电流 (Isup)：40 mA最大供电电压 (Vsup)：3.96 V
最小供电电压 (Vsup)：2.8 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：OTHER
端子形式：GULL WING端子节距：0.4 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

LPTM10-1247-3TG128C 数据手册

 浏览型号LPTM10-1247-3TG128C的Datasheet PDF文件第2页浏览型号LPTM10-1247-3TG128C的Datasheet PDF文件第3页浏览型号LPTM10-1247-3TG128C的Datasheet PDF文件第4页浏览型号LPTM10-1247-3TG128C的Datasheet PDF文件第5页浏览型号LPTM10-1247-3TG128C的Datasheet PDF文件第6页浏览型号LPTM10-1247-3TG128C的Datasheet PDF文件第7页 
Platform Manager  
In-System Programmable Power and Digital  
Board Management  
February 2012  
Data Sheet DS1036  
Features  
Block Diagram  
Precision Voltage Monitoring Increases  
10-Bit  
12 Analog  
Voltage  
Monitor  
Inputs  
Margin/Trim  
Reliability  
ADC  
• 12 independent analog monitor inputs  
• Differential inputs for remote ground sense  
• Two programmable threshold comparators per  
analog input  
MOSFET  
Drivers  
48-Macrocell  
CPLD  
Digital  
Inputs  
Open Drain  
Outputs  
• Hardware window comparison  
• 10-bit ADC for I2C monitoring  
Power  
FPGA  
4 Timers  
High-Voltage FET Drivers Enable  
Integration  
JTAG I/O  
JTAG I/O  
• Power supply ramp up/down control  
• Programmable current and voltage output  
• Independently configurable for FET control or  
digital output  
Configuration  
Memory  
640-LUT  
FPGA  
Digital I/O  
Power  
II2C/SMBus  
Power Supply Margin and Trim Functions  
• Trim and margin up to eight power supplies  
• Dynamic voltage control through I2C  
• Independent Digital Closed-Loop Trim function  
for each output  
Programmable Timers Increase Control  
Flexibility  
• Four independent timers  
• 32 s to 2 second intervals for timing sequences  
PLD Resources Integrate Power and Digital  
Description  
The Lattice Platform Manager integrates board power  
management (hot-swap, sequencing, monitoring, reset  
generation, trimming and margining) and digital board  
management functions (reset tree, non-volatile error  
logging, glue logic, board digital signal monitoring and  
control, system bus interface, etc.) into a single inte-  
grated solution.  
Functions  
• 48-macrocell CPLD  
• 640 LUT4s FPGA  
• Up to 107 digital I/Os  
The Platform Manager device provides 12 independent  
analog input channels to monitor up to 12 power supply  
test points. Up to 12 of these input channels can be  
monitored through differential inputs to support remote  
ground sensing. Each of the analog input channels is  
monitored through two independently programmable  
comparators to support both high/low and in-bounds/  
out-of-bounds (window-compare) monitor functions. Up  
to six general purpose 5V tolerant digital inputs are also  
provided for miscellaneous control functions.  
• Up to 6.1 Kbits distributed RAM  
Programmable sysIO™ Buffer Supports a  
Range of Interfaces  
• LVCMOS 3.3/2.5/1.8/1.5/1.2  
• LVTTL  
System-Level Support  
• Single 3.3V supply operation  
• Industrial temperature range: -40°C to +85°C  
In-System Programmability Reduces Risk  
• Integrated non-volatile configuration memory  
• JTAG programming interface  
Package Options  
There are 16 open-drain digital outputs that can be  
used for controlling DC-DC converters, low-drop-out  
regulators (LDOs) and opto-couplers, as well as for  
supervisory and general purpose logic interface func-  
tions. Four of these outputs (HVOUT1-HVOUT4) may  
be configured as high-voltage MOSFET drivers. In high-  
voltage mode these outputs can provide up to 12V for  
driving the gates of n-channel MOSFETs so that they  
can be used as high-side power switches controlling the  
supplies with a programmable ramp rate for both ramp  
up and ramp down.  
• 128-pin TQFP  
• 208-ball ftBGA  
• RoHS compliant and halogen-free  
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other  
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without  
notice.  
www.latticesemi.com  
1
DS1036_01.3  
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