Platform Manager
In-System Programmable Power and Digital
Board Management
February 2012
Data Sheet DS1036
Features
Block Diagram
Precision Voltage Monitoring Increases
10-Bit
12 Analog
Voltage
Monitor
Inputs
Margin/Trim
Reliability
ADC
• 12 independent analog monitor inputs
• Differential inputs for remote ground sense
• Two programmable threshold comparators per
analog input
MOSFET
Drivers
48-Macrocell
CPLD
Digital
Inputs
Open Drain
Outputs
• Hardware window comparison
• 10-bit ADC for I2C monitoring
Power
FPGA
4 Timers
High-Voltage FET Drivers Enable
Integration
JTAG I/O
JTAG I/O
• Power supply ramp up/down control
• Programmable current and voltage output
• Independently configurable for FET control or
digital output
Configuration
Memory
640-LUT
FPGA
Digital I/O
Power
II2C/SMBus
Power Supply Margin and Trim Functions
• Trim and margin up to eight power supplies
• Dynamic voltage control through I2C
• Independent Digital Closed-Loop Trim function
for each output
Programmable Timers Increase Control
Flexibility
• Four independent timers
• 32 s to 2 second intervals for timing sequences
PLD Resources Integrate Power and Digital
Description
The Lattice Platform Manager integrates board power
management (hot-swap, sequencing, monitoring, reset
generation, trimming and margining) and digital board
management functions (reset tree, non-volatile error
logging, glue logic, board digital signal monitoring and
control, system bus interface, etc.) into a single inte-
grated solution.
Functions
• 48-macrocell CPLD
• 640 LUT4s FPGA
• Up to 107 digital I/Os
The Platform Manager device provides 12 independent
analog input channels to monitor up to 12 power supply
test points. Up to 12 of these input channels can be
monitored through differential inputs to support remote
ground sensing. Each of the analog input channels is
monitored through two independently programmable
comparators to support both high/low and in-bounds/
out-of-bounds (window-compare) monitor functions. Up
to six general purpose 5V tolerant digital inputs are also
provided for miscellaneous control functions.
• Up to 6.1 Kbits distributed RAM
Programmable sysIO™ Buffer Supports a
Range of Interfaces
• LVCMOS 3.3/2.5/1.8/1.5/1.2
• LVTTL
System-Level Support
• Single 3.3V supply operation
• Industrial temperature range: -40°C to +85°C
In-System Programmability Reduces Risk
• Integrated non-volatile configuration memory
• JTAG programming interface
Package Options
There are 16 open-drain digital outputs that can be
used for controlling DC-DC converters, low-drop-out
regulators (LDOs) and opto-couplers, as well as for
supervisory and general purpose logic interface func-
tions. Four of these outputs (HVOUT1-HVOUT4) may
be configured as high-voltage MOSFET drivers. In high-
voltage mode these outputs can provide up to 12V for
driving the gates of n-channel MOSFETs so that they
can be used as high-side power switches controlling the
supplies with a programmable ramp rate for both ramp
up and ramp down.
• 128-pin TQFP
• 208-ball ftBGA
• RoHS compliant and halogen-free
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
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