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LPC811M001JDH16 PDF预览

LPC811M001JDH16

更新时间: 2024-11-23 12:46:35
品牌 Logo 应用领域
恩智浦 - NXP 闪存微控制器静态存储器
页数 文件大小 规格书
71页 533K
描述
32-bit ARM Cortex-M0 microcontroller; up to 16 kB flash and 4 kB SRAM

LPC811M001JDH16 技术参数

生命周期:Active包装说明:TSSOP,
Reach Compliance Code:unknown风险等级:5.76
具有ADC:NO地址总线宽度:
位大小:32最大时钟频率:25 MHz
DAC 通道:NODMA 通道:NO
外部数据总线宽度:JESD-30 代码:R-PDSO-G16
长度:5 mmI/O 线路数量:14
端子数量:16片上程序ROM宽度:8
最高工作温度:105 °C最低工作温度:-40 °C
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCHRAM(字节):2048
ROM(单词):8192ROM可编程性:FLASH
座面最大高度:1.1 mm速度:30 MHz
最大供电电压:3.6 V最小供电电压:1.8 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLER, RISCBase Number Matches:1

LPC811M001JDH16 数据手册

 浏览型号LPC811M001JDH16的Datasheet PDF文件第2页浏览型号LPC811M001JDH16的Datasheet PDF文件第3页浏览型号LPC811M001JDH16的Datasheet PDF文件第4页浏览型号LPC811M001JDH16的Datasheet PDF文件第5页浏览型号LPC811M001JDH16的Datasheet PDF文件第6页浏览型号LPC811M001JDH16的Datasheet PDF文件第7页 
LPC81xM  
32-bit ARM Cortex-M0+ microcontroller; up to 16 kB flash and  
4 kB SRAM  
Rev. 3 — 29 July 2013  
Product data sheet  
1. General description  
The LPC81xM are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at  
CPU frequencies of up to 30 MHz. The LPC81xM support up to 16 kB of flash memory  
and 4 kB of SRAM.  
The peripheral complement of the LPC81xM includes a CRC engine, one I2C-bus  
interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up  
timer, and state-configurable timer, one comparator, function-configurable I/O ports  
through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O  
pins.  
2. Features and benefits  
System:  
ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz with  
single-cycle multiplier and fast single-cycle I/O port.  
ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).  
System tick timer.  
Serial Wire Debug (SWD) and JTAG boundary scan modes supported.  
Micro Trace Buffer (MTB) supported.  
Memory:  
Up to 16 kB on-chip flash programming memory with 64 Byte page write and erase.  
Up to 4 kB SRAM.  
ROM API support:  
Boot loader.  
USART drivers.  
I2C drivers.  
Power profiles.  
Flash In-Application Programming (IAP) and In-System Programming (ISP).  
Digital peripherals:  
High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 18  
General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,  
programmable open-drain mode, input inverter, and glitch filter.  
High-current source output driver (20 mA) on four pins.  
High-current sink driver (20 mA) on two true open-drain pins.  
GPIO interrupt generation capability with boolean pattern-matching feature on eight  
GPIO inputs.  
Switch matrix for flexible configuration of each I/O pin function.  

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