LP2998
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SNVS521I –DECEMBER 2007–REVISED APRIL 2013
LP2998 DDR-I and DDR-II Termination Regulator
Check for Samples: LP2998
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FEATURES
DESCRIPTION
The LP2998 linear regulator is designed to meet
JEDEC SSTL-2 and JEDEC SSTL-18 specifications
for termination of DDR1-SDRAM and DDR-II
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Source and Sink Current
Low Output Voltage Offset
No External Resistors Required
Linear Topology
memory. The device contains
a
high-speed
operational amplifier to provide excellent response to
load transients. The output stage prevents shoot
through while delivering 1.5A continuous current as
required for DDR1-SDRAM termination, and 0.5A
continuous current as required for DDR-II termination.
The LP2998 also incorporates a VSENSE pin to provide
superior load regulation and a VREF output as a
reference for the chipset and DIMMs.
Suspend to Ram (STR) Functionality
Low External Component Count
Thermal Shutdown
Available in SOIC-8, SO PowerPAD-8 Packages
APPLICATIONS
An additional feature found on the LP2998 is an
active low shutdown (SD) pin that provides Suspend
To RAM (STR) functionality. When SD is pulled low,
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DDR-I, DDR-II and DDR-III Termination Voltage
SSTL-18 Termination
the VTT output will tri-state providing
a
high
SSTL-2 and SSTL-3 Termination
HSTL Termination
impedance output, while VREF remains active. A
power savings advantage can be obtained in this
mode through lower quiescent current.
Typical Application Circuit
LP2998
V
= 0.9V
V
REF
REF
SD
AV
SD
+
+
C
C
REF
AV = 2.5V
IN
IN
V
VSENSE
V
= 1.8V
DDQ
DDQ
PV
IN
V
= 0.9V
V
TT
TT
+
GND
C
OUT
IN
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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