Datasheet > LMU112PC50

LMU112PC50

更新时间： 2024-09-23 22:31:11

品牌	Logo	应用领域
逻辑 - LOGIC		/
页数	文件大小	规格书
6页	49K
描述
12 x 12-bit Parallel Multiplier

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LMU112PC50 数据手册

LMU112

DEVICES INCORPORATED

12 x 12-bit Parallel Multiplier

LMU112

12 x 12-bit Parallel Multiplier

DEVICES INCORPORATED

FEATURES

DESCRIPTION

The LMU112 is a high-speed, low

power 12-bit parallel multiplier built

using advanced CMOS technology.

The LMU112 is pin and functionally

which is loaded along with the B

operands. The operands are specified

to be in two’s complement format

when TC is asserted and unsigned

❑ 25 ns Worst-Case Multiply Time

❑ Low Power CMOS Technology

❑ Replaces Fairchild MPY112K

❑ Two’s Complement or Unsigned

compatible with Fairchilds’s MPY112K. magnitude when TC is deasserted.

Operands

Mixed mode operation is not allowed.

The A and B input operands are

❑ Three-State Outputs

loaded into their respective registers

on the rising edge of the separate

clock inputs (CLK A and CLK B).

Two’s complement or unsigned

magnitude operands are accommo-

For two’s complement operands, the

17 most significant bits at the output

of the asynchronous multiplier array

are shifted one bit position to the left.

This is done to discard the redundant

❑ Package Styles Available:

• 48-pin PDIP

• 52-pin PLCC, J-Lead

dated via the operand control bit (TC) copy of the sign-bit, which is in the

most significant bit position, and

extend the bit precision by one bit.

The result is then truncated to the 16

MSB’s and loaded into the output

LMU112 BLOCK DIAGRAM

11-0

B11-0

A REGISTER

B REGISTER

The contents of the output register are

made available via three-state buffers

by asserting OE. When OE is de-

asserted, the outputs (R23-8) are in the

high impedance state.

CLK A

CLK B

FORMAT ADJUST

RESULT REGISTER

23-8

Multipliers

08/16/2000–LDS.112-K

12 3 4 5 6

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