ADVANCE INFORMATION
May 2002
LM9628 Color CMOS Image Sensor VGA 30 FPS
General Description
Applications
The LM9628 is a high performance, low power, 1/3” VGA CMOS
Active Pixel Sensor capable of capturing color digital still or
motion images and converting them to a digital data stream.
f Dual Mode Camera
f Digital Still Camera
f Security Cameras
f Machine Vision
f Automotive
In addition to the active pixel array, an on-chip 12 bit A/D conver-
tor, fixed pattern noise elimination circuits, a video gain and sep-
arate color gain amplifier are provided. Furthermore, an
integrated programmable smart timing and control circuit allows
the user maximum flexibility in adjusting integration time, active
window size, gain and frame rate. Various control, timing and
power modes are also provided.
Key Specifications
Array Format
Total:
Active: 648H x 488 V
664H x 504V
Effective Image Area
Total: 4.98mm x 3.78 mm
Active: 4.86 mm x 3.66 mm
The excellent linear dynamic range of the sensor can be
extended to above 100dB by programming
a non linear
Optical Format
Pixel Size
1/3“
response curve that matches the response of the human eye.
7.5mm x 7.5mm
8,10 & 12 Bit Digital
30 frames per second
Video Outputs
Frame Rate
Features
f Video or snapshot operations
Dynamic Range
62dB in linear mode
f Programmable pixel clock, inter-frame and inter-line delays.
f Programmable partial or full frame integration
f Programmable gain and individual color gain adjustment
f Horizontal & vertical sub-sampling (2:1 & 4:2)
f Programmable digital video response curve
f Windowing
110dB in non linear mode
Electronic Shutter
FPN
Rolling reset
0.1%
PRMU
1.5%
Sensitivity
2.7 V/lux.s
27%
f External snapshot trigger & event synchronisation signals
f Auto black level compensation
Quantum Efficiency
Fill Factor
f Flexible digital video read-out supporting programmable:
47%
-
-
polarity for synchronisation and pixel clock signals
leading edge adjustment for horizontal synchronization
Color Mosaic
Package
Bayer pattern
48 CLCC
3.3 V +/-10%
120 mW
2
f Programmable via 2 wire I C compatible serial interface
f Power on reset & power down mode
Single Supply
Power Consumption
Operating Temp
o
-40 to 85 C
Overall Chip Block Diagram
oe
R
d[11:0]
pclk
12 Bit A/D
AMP
G
B
mux
Row Address
Decoder
hsync
vsync
APS Array
POR
Vertical
Timing
Horizontal
Timing
Reset
Gen
Row Address
Gen
Gain
Control
sda
sclk
2
I C Compatible
Serial I/F
Register Bank
Power
Control
Controller
(sequencer)
Clock Gen
sadr
Master Timer
reset mclk
extsync snapshot
pdwn
ã 2002 National Semiconductor Corporation
www.national.com