LM97593EB

更新时间： 2024-11-19 03:51:39

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
50页	3837K
描述
Dual ADC / Digital Tuner / AGC

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LM97593EB 数据手册

March 12, 2008

LM97593

Dual ADC / Digital Tuner / AGC

General Description

Features

The LM97593 Dual ADC / Digital Tuner / AGC IC is a two

channel digital downconverter (DDC) with integrated 12-bit

analog-to-digital converters (ADCs) and automatic gain con-

trol (AGC). The LM97593 further enhances National’s Diver-

sity Receiver Chipset (DRCS) by integrating a wide-band-

width dual ADC core with the DDC. The complete DRCS

includes one LM97593 Dual ADC / Digital Tuner / AGC and

two CLC5526 digitally controlled variable gain amplifiers (DV-

GAs). This system allows direct IF sampling of signals up to

300MHz for enhanced receiver performance and reduced

system costs. A block diagram for a DRCS-based narrow-

band communications system is shown in Figure 1.

100% Software compatible with the CLC5903

■

Pin compatible with the CLC5903 except for the analog

input and reference section

123 dB dynamic range with CLC5526 DVGA (200kHz)

On-chip precision reference

■

User Programmable AGC with enhanced Power Detector

Channel Filters include a Fourth Order CIC followed by 21-

tap and 63-tap Symmetric FIRs

Flexible output formats

Serial and Parallel output ports

JTAG Boundary Scan

8-bit Microprocessor Interface

128 pin PQFP

■

The LM97593 offers high dynamic range digital tuning and

filtering based on hard-wired digital signal processing (DSP)

technology. Each channel has independent tuning, phase off-

set, filter coefficients, and gain settings. Channel filtering is

performed by a series of three filters. The first is a 4-stage

Cascaded Integrator Comb (CIC) filter with a programmable

decimation ratio from 8 to 2048. Next there are two symmetric

FIR filters, a 21-tap and a 63-tap, both with independent pro-

grammable coefficients. The first FIR filter decimates the data

by 2, the second FIR decimates by either 2 or 4. Channel filter

bandwidth at 52MSPS ranges from ±650kHz down to

±1.3kHz. At 65MSPS, the maximum bandwidth increases to

±812kHz.

Key Specifications

Internal ADC Resolution

Sample Rate

SNR (f_IN= 250MHz, 11-bit, Nyquist)

SNR (f_IN= 250MHz, 200kHz)

SFDR (f_IN= 250MHz, 11-bit, Nyquist)

Full Power Bandwidth

Power Consumption (65MSPS)

12 Bits

65 MSPS

■

62 dBFS (typ)

83 dBFS (typ)

68 dBFS (typ)

650 MHz (typ)

560 mW (typ)

■

The LM97593’s AGC controller monitors the ADC output and

controls the ADC input signal level by adjusting the DVGA

setting. AGC threshold, deadband+hysteresis, and the loop

time constant are user defined. Total dynamic range of

greater than 123dB full-scale signal to noise in a 200kHz

bandwidth can be achieved with the Diversity Receiver

Chipset.

Applications

Cellular Basestations

■

GSM / GPRS / EDGE / GSM Phase 2 Receivers

Satellite Receivers

■

Wireless Local Loop Receivers

Digital Communications

Block Diagram 1

30008701

FIGURE 1. Diversity Receiver Chipset Block Diagram

300087

www.national.com

12 3 4 5 6 7...50

中文翻译

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与LM97593EB相关器件

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LM97593VH	NSC	获取价格	Dual ADC / Digital Tuner / AGC
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LM9800CCV	NSC	获取价格	8-Bit Greyscale/24-Bit Color Linear CCD Sensor Processor
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LM9801CCV	NSC	获取价格	Greyscale/24-Bit Color Linear CCD Sensor Processor
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LM9801CCVFX	TI	获取价格	SPECIALTY ANALOG CIRCUIT, PQFP52, TQFP-52
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