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LM97593

更新时间： 2024-01-15 14:43:54
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
50页 3837K
描述
Dual ADC / Digital Tuner / AGC

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LM97593 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：FQFP,针数：128
Reach Compliance Code：compliantECCN代码：5A991.B
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.1商用集成电路类型：CONSUMER CIRCUIT
JESD-30 代码：R-PQFP-G128JESD-609代码：e3
长度：20 mm湿度敏感等级：3
功能数量：1端子数量：128
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：FQFP
封装形状：RECTANGULAR封装形式：FLATPACK, FINE PITCH
峰值回流温度（摄氏度）：245座面最大高度：3.4 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

LM97593 数据手册

 浏览型号LM97593的Datasheet PDF文件第2页浏览型号LM97593的Datasheet PDF文件第3页浏览型号LM97593的Datasheet PDF文件第4页浏览型号LM97593的Datasheet PDF文件第5页浏览型号LM97593的Datasheet PDF文件第6页浏览型号LM97593的Datasheet PDF文件第7页 
March 12, 2008  
LM97593  
Dual ADC / Digital Tuner / AGC  
General Description  
Features  
The LM97593 Dual ADC / Digital Tuner / AGC IC is a two  
channel digital downconverter (DDC) with integrated 12-bit  
analog-to-digital converters (ADCs) and automatic gain con-  
trol (AGC). The LM97593 further enhances National’s Diver-  
sity Receiver Chipset (DRCS) by integrating a wide-band-  
width dual ADC core with the DDC. The complete DRCS  
includes one LM97593 Dual ADC / Digital Tuner / AGC and  
two CLC5526 digitally controlled variable gain amplifiers (DV-  
GAs). This system allows direct IF sampling of signals up to  
300MHz for enhanced receiver performance and reduced  
system costs. A block diagram for a DRCS-based narrow-  
band communications system is shown in Figure 1.  
100% Software compatible with the CLC5903  
■
■
Pin compatible with the CLC5903 except for the analog  
input and reference section  
123 dB dynamic range with CLC5526 DVGA (200kHz)  
On-chip precision reference  
■
■
■
■
User Programmable AGC with enhanced Power Detector  
Channel Filters include a Fourth Order CIC followed by 21-  
tap and 63-tap Symmetric FIRs  
Flexible output formats  
Serial and Parallel output ports  
JTAG Boundary Scan  
8-bit Microprocessor Interface  
128 pin PQFP  
■
■
■
■
■
The LM97593 offers high dynamic range digital tuning and  
filtering based on hard-wired digital signal processing (DSP)  
technology. Each channel has independent tuning, phase off-  
set, filter coefficients, and gain settings. Channel filtering is  
performed by a series of three filters. The first is a 4-stage  
Cascaded Integrator Comb (CIC) filter with a programmable  
decimation ratio from 8 to 2048. Next there are two symmetric  
FIR filters, a 21-tap and a 63-tap, both with independent pro-  
grammable coefficients. The first FIR filter decimates the data  
by 2, the second FIR decimates by either 2 or 4. Channel filter  
bandwidth at 52MSPS ranges from ±650kHz down to  
±1.3kHz. At 65MSPS, the maximum bandwidth increases to  
±812kHz.  
Key Specifications  
Internal ADC Resolution  
Sample Rate  
SNR (fIN = 250MHz, 11-bit, Nyquist)  
SNR (fIN = 250MHz, 200kHz)  
SFDR (fIN = 250MHz, 11-bit, Nyquist)  
Full Power Bandwidth  
Power Consumption (65MSPS)  
12 Bits  
65 MSPS  
■
■
62 dBFS (typ)  
83 dBFS (typ)  
68 dBFS (typ)  
650 MHz (typ)  
560 mW (typ)  
■
■
■
■
■
The LM97593’s AGC controller monitors the ADC output and  
controls the ADC input signal level by adjusting the DVGA  
setting. AGC threshold, deadband+hysteresis, and the loop  
time constant are user defined. Total dynamic range of  
greater than 123dB full-scale signal to noise in a 200kHz  
bandwidth can be achieved with the Diversity Receiver  
Chipset.  
Applications  
Cellular Basestations  
■
GSM / GPRS / EDGE / GSM Phase 2 Receivers  
Satellite Receivers  
■
■
■
■
Wireless Local Loop Receivers  
Digital Communications  
Block Diagram 1  
30008701  
FIGURE 1. Diversity Receiver Chipset Block Diagram  
© 2008 National Semiconductor Corporation  
300087  
www.national.com  
1234567...50

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