LM20133, LM20133Q
www.ti.com
SNVS526F –OCTOBER 2007–REVISED MARCH 2013
3A, PowerWise® Synchronous Buck Regulator with Input Synchronization
Check for Samples: LM20133, LM20133Q
1
FEATURES
DESCRIPTION
The LM20133 is a full featured synchronous buck
2
•
LM20133Q is AEC-Q100 Qualified and
regulator capable of delivering up to 3A of continuous
output current. The current mode control loop can be
compensated to be stable with virtually any type of
output capacitor. For most cases, compensating the
device only requires two external components,
providing maximum flexibility and ease of use. The
device is optimized to work over the input voltage
range of 2.95V to 5.5V making it suited for a wide
variety of low voltage systems.
Manufactured on an Automotive Grade Flow
•
•
Input Voltage Range 2.95V to 5.5V
Accurate Current Limit Minimizes Inductor
Size
•
•
•
•
•
•
•
•
•
97% Peak Efficiency
Frequency Synchronization Pin
32 mΩ Integrated FET Switches
Starts up into Pre-Biased Loads
Output Voltage Tracking
The device features internal over voltage protection
(OVP) and over current protection (OCP) circuits for
increased system reliability. A precision enable pin
and integrated UVLO allows the turn on of the device
to be tightly controlled and sequenced. Start-up
inrush currents are limited by both an internally fixed
and externally adjustable Soft-Start circuit. Fault
detection and supply sequencing is possible with the
integrated power good circuit.
Peak Current Mode Control
Adjustable Soft-Start with External Capacitor
Precision Enable Pin with Hysteresis
Integrated OVP, UVLO, Power Good and
Thermal Shutdown
•
HTSSOP 16-Pin Exposed Pad Package
The switching frequency of the LM20133 can be
synchronized to an external clock by use of the
SYNC pin. The SYNC pin is capable of synchronizing
to input signals ranging from 500 kHz to 1.5 MHz.
APPLICATIONS
•
•
•
Simple to Design, High Efficiency Point of
Load Regulation from a 5V or 3.3V bus
The LM20133 is designed to work well in multi-rail
power supply architectures. The output voltage of the
device can be configured to track a higher voltage rail
using the SS/TRK pin. If the output of the LM20133 is
pre-biased at startup it will not sink current to pull the
output low until the internal soft-start ramp exceeds
the voltage at the feedback pin.
High Performance DSPs, FPGAs, ASICs and
Microprocessors
Broadband, Networking and Optical
Communications Infrastructure
Typical Application Circuit
L
LM20133
V
OUT
SW
FB
V
IN
PVIN
R
R
FB1
EN
C
IN
R
F
C
OUT
AVIN
FB2
PGOOD
VCC
SYNC
COMP
C
F
C
VCC
SS/TRK
AGND
R
C1
PGND
C
SS
C
C1
(optional)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated