Register Description (Continued)
Bits 0–2
HORIZONTAL INTERVAL REGISTERS
The Horizontal Interval Registers determine the number of
clock cycles per line and the characteristics of the Horizon-
tal Sync and Blank pulses.
B
B
B
VCBLANK VCSYNC HBLHDR HSYNVDR
0
2
1
0
0
0
CBLANK
CSYNC HGATE
VGATE
(DEFAULT)
REG1Ð Horizontal Front Porch
0
0
0
0
1
1
1
0
1
VBLANK
CBLANK
VBLANK
CSYNC HBLANK
VGATE
HSYNC
HSYNC
REG2Ð Horizontal Sync Pulse End Time
REG3Ð Horizontal Blanking Width
VSYNC
HGATE
VSYNC HBLANK
Ý
REG4Ð Horizontal Interval Width
of Clocks per Line
1
1
1
1
0
0
1
1
0
1
0
1
CBLANK
VBLANK
CBLANK
VBLANK
CSYNC CURSOR
CSYNC HBLANK
VINT
VINT
VERTICAL INTERVAL REGISTERS
The Vertical Interval Registers determine the number of
lines per frame, and the characteristics of the Vertical Blank
and Sync Pulses.
VSYNC CURSOR HSYNC
VSYNC HBLANK
HSYNC
Bits 3–4
REG5Ð Vertical Front Porch
REG6Ð Vertical Sync Pulse End Time
REG7Ð Vertical Blanking Width
B
B
Mode of Operation
4
3
0
0
Interlaced Double Serration and
Equalization
Ý
REG8Ð Vertical Interval Width
of Lines per Frame
(DEFAULT)
EQUALIZATION AND SERRATION PULSE
SPECIFICATION REGISTERS
0
1
1
1
0
1
Non Interlaced Double Serration
Illegal State
These registers determine the width of equalization and ser-
ration pulses and the vertical interval over which they occur.
Non Interlaced Single Serration
and Equalization
REG 9Ð Equalization Pulse Width End Time
REG10Ð Serration Pulse Width End Time
Double Equalization and Serration mode will output equali-
zation and serration pulses at twice the HSYNC frequency
(i.e., 2 equalization or serration pulses for every HSYNC
pulse). Single Equalization and Serration mode will output
an equalization or serration pulse for every HSYNC pulse. In
Interlaced mode equalization and serration pulses will be
output during the VBLANK period of every odd and even
field. Interlaced Single Equalization and Serration mode is
not possible with this part.
REG11Ð Equalization/Serration Pulse Vertical
Interval Start Time
REG12Ð Equalization/Serration Pulse Vertical
Interval End Time
VERTICAL INTERRUPT SPECIFICATION REGISTERS
These Registers determine the width of the Vertical Inter-
rupt signal if used.
Bits 5–8
REG13Ð Vertical Interrupt Activate Time
REG14Ð Vertical Interrupt Deactivate Time
Bits 5 through 8 control the polarity of the outputs. A value
of zero in these bit locations indicates an output pulse active
LOW. A value of 1 indicates an active HIGH pulse.
CURSOR LOCATION REGISTERS
B5Ð VCBLANK Polarity
B6Ð VCSYNC Polarity
B7Ð HBLHDR Polarity
B8Ð HSYNVDR Polarity
These 4 registers determine the cursor position location, or
they generate separate Horizontal and Vertical Gating sig-
nals.
REG15Ð Horizontal Cursor Position Start Time
REG16Ð Horizontal Cursor Position End Time
REG17Ð Vertical Cursor Position Start Time
REG18Ð Vertical Cursor Position End Time
Bits 9–11
Bits 9 through 11 enable several different features of the
device.
B9Ð Enable Equalization/Serration Pulses (0)
Disable Equalization/Serration Pulses (1)
Signal Specification
HORIZONTAL SYNC AND BLANK
SPECIFICATIONS
B10Ð Disable System Clock (0)
Enable System Clock (1)
Default values for B10 are ‘‘0’’ in the ’ACT715/
LM1882 and ‘‘1’’ in the ’ACT715-R/LM1882-R.
All horizontal signals are defined by a start and end time.
The start and end times are specified in number of clock
cycles per line. The start of the horizontal line is considered
pulse 1 not 0. All values of the horizontal timing registers are
referenced to the falling edge of the Horizontal Blank signal
B11Ð Disable Counter Test Mode (0)
Enable Counter Test Mode (1)
This bit is not intended for the user but is for internal
testing only.
Ý
(see Figure 1 ). Since the first CLOCK edge, CLOCK 1,
causes the first falling edge of the Horizontal Blank refer-
ence pulse, edges referenced to this first Horizontal edge
a
are n
1 CLOCKs away, where ‘‘n’’ is the width of the
timing in question. Registers 1, 2, and 3 are programmed in
this manner. The horizontal counters start at 1 and count
until HMAX. The value of HMAX must be divisible by 2. This
3