Datasheet > LM1882E/883

LM1882E/883

更新时间： 2024-01-12 08:15:54

品牌	Logo	应用领域
德州仪器 - TI		商用集成电路
页数	文件大小	规格书
16页	236K
描述
SPECIALTY CONSUMER CIRCUIT, CQCC20, CERAMIC, LCC-20

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中文翻译

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技术参数
数据手册

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LM1882E/883 技术参数

生命周期：	Obsolete	包装说明：	QCCN,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.65	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	S-CQCC-N20	长度：	8.89 mm
功能数量：	1	端子数量：	20
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	QCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER
认证状态：	Not Qualified	座面最大高度：	1.905 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
表面贴装：	YES	温度等级：	MILITARY
端子形式：	NO LEAD	端子节距：	1.27 mm
端子位置：	QUAD	宽度：	8.89 mm
Base Number Matches：	1

LM1882E/883 数据手册

Bits 0–2

HORIZONTAL INTERVAL REGISTERS

The Horizontal Interval Registers determine the number of

clock cycles per line and the characteristics of the Horizon-

tal Sync and Blank pulses.

VCBLANK VCSYNC HBLHDR HSYNVDR

CBLANK

CSYNC HGATE

VGATE

(DEFAULT)

REG1Ð Horizontal Front Porch

VBLANK

CBLANK

VBLANK

CSYNC HBLANK

VGATE

HSYNC

REG2Ð Horizontal Sync Pulse End Time

REG3Ð Horizontal Blanking Width

VSYNC

HGATE

VSYNC HBLANK

REG4Ð Horizontal Interval Width

of Clocks per Line

CBLANK

VBLANK

CBLANK

VBLANK

CSYNC CURSOR

CSYNC HBLANK

VINT

VERTICAL INTERVAL REGISTERS

The Vertical Interval Registers determine the number of

lines per frame, and the characteristics of the Vertical Blank

and Sync Pulses.

VSYNC CURSOR HSYNC

VSYNC HBLANK

HSYNC

Bits 3–4

REG5Ð Vertical Front Porch

REG6Ð Vertical Sync Pulse End Time

REG7Ð Vertical Blanking Width

Mode of Operation

Interlaced Double Serration and

Equalization

REG8Ð Vertical Interval Width

of Lines per Frame

(DEFAULT)

EQUALIZATION AND SERRATION PULSE

SPECIFICATION REGISTERS

Non Interlaced Double Serration

Illegal State

These registers determine the width of equalization and ser-

ration pulses and the vertical interval over which they occur.

Non Interlaced Single Serration

and Equalization

REG 9Ð Equalization Pulse Width End Time

REG10Ð Serration Pulse Width End Time

Double Equalization and Serration mode will output equali-

zation and serration pulses at twice the HSYNC frequency

(i.e., 2 equalization or serration pulses for every HSYNC

pulse). Single Equalization and Serration mode will output

an equalization or serration pulse for every HSYNC pulse. In

Interlaced mode equalization and serration pulses will be

output during the VBLANK period of every odd and even

field. Interlaced Single Equalization and Serration mode is

not possible with this part.

REG11Ð Equalization/Serration Pulse Vertical

Interval Start Time

REG12Ð Equalization/Serration Pulse Vertical

Interval End Time

VERTICAL INTERRUPT SPECIFICATION REGISTERS

These Registers determine the width of the Vertical Inter-

rupt signal if used.

Bits 5–8

REG13Ð Vertical Interrupt Activate Time

REG14Ð Vertical Interrupt Deactivate Time

Bits 5 through 8 control the polarity of the outputs. A value

of zero in these bit locations indicates an output pulse active

LOW. A value of 1 indicates an active HIGH pulse.

CURSOR LOCATION REGISTERS

B5Ð VCBLANK Polarity

B6Ð VCSYNC Polarity

B7Ð HBLHDR Polarity

B8Ð HSYNVDR Polarity

These 4 registers determine the cursor position location, or

they generate separate Horizontal and Vertical Gating sig-

nals.

REG15Ð Horizontal Cursor Position Start Time

REG16Ð Horizontal Cursor Position End Time

REG17Ð Vertical Cursor Position Start Time

REG18Ð Vertical Cursor Position End Time

Bits 9–11

Bits 9 through 11 enable several different features of the

device.

B9Ð Enable Equalization/Serration Pulses (0)

Disable Equalization/Serration Pulses (1)

Signal Specification

HORIZONTAL SYNC AND BLANK

SPECIFICATIONS

B10Ð Disable System Clock (0)

Enable System Clock (1)

Default values for B10 are ‘‘0’’ in the ’ACT715/

LM1882 and ‘‘1’’ in the ’ACT715-R/LM1882-R.

All horizontal signals are defined by a start and end time.

The start and end times are specified in number of clock

cycles per line. The start of the horizontal line is considered

pulse 1 not 0. All values of the horizontal timing registers are

referenced to the falling edge of the Horizontal Blank signal

B11Ð Disable Counter Test Mode (0)

Enable Counter Test Mode (1)

This bit is not intended for the user but is for internal

testing only.

(see Figure 1 ). Since the first CLOCK edge, CLOCK 1,

causes the first falling edge of the Horizontal Blank refer-

ence pulse, edges referenced to this first Horizontal edge

are n

1 CLOCKs away, where ‘‘n’’ is the width of the

timing in question. Registers 1, 2, and 3 are programmed in

this manner. The horizontal counters start at 1 and count

until HMAX. The value of HMAX must be divisible by 2. This

1 234 5 6 7...16

中文翻译

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与LM1882E/883相关器件

型号	品牌	获取价格	描述	数据表
LM1882EV	TI	获取价格	SPECIALTY CONSUMER CIRCUIT, PQCC20, PLASTIC, LCC-20
LM1882J/883	TI	获取价格	SPECIALTY CONSUMER CIRCUIT, CDIP20, CERAMIC, DIP-20
LM1882L	TI	获取价格	SPECIALTY CONSUMER CIRCUIT, CQCC20, CERAMIC, LCC-20
LM1882P	TI	获取价格	SPECIALTY CONSUMER CIRCUIT, PDIP20, PLASTIC, DIP-20
LM1882-R	NSC	获取价格	Programmable Video Sync Generator
LM1882RCM	ETC	获取价格	TV/Video Sync Circuit
LM1882-RCM	NSC	获取价格	Programmable Video Sync Generator
LM1882-RCMX	TI	获取价格	SPECIALTY CONSUMER CIRCUIT, PDSO20, SOIC-20
LM1882RCN	ETC	获取价格	TV/Video Sync Circuit
LM1882-RCN	NSC	获取价格	Programmable Video Sync Generator

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