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LM1882J/883 PDF预览

LM1882J/883

更新时间： 2024-11-23 15:37:23
品牌 Logo 应用领域
德州仪器 - TI 商用集成电路
页数 文件大小 规格书
16页 236K
描述
SPECIALTY CONSUMER CIRCUIT, CDIP20, CERAMIC, DIP-20

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中文翻译

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LM1882J/883 技术参数

生命周期：Obsolete包装说明：DIP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.65商用集成电路类型：CONSUMER CIRCUIT
JESD-30 代码：R-GDIP-T20长度：24.51 mm
功能数量：1端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
表面贴装：NO温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

LM1882J/883 数据手册

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March 1995  
LM1882 54ACT/74ACT715  
#
LM1882-R 54ACT/74ACT715-R  
#
Programmable Video Sync Generator  
’ACT715-R/LM1882-R is mask programmed to default to a  
Clock Enabled state. Bit 10 of the Status Register defaults  
to a logic ‘‘1’’. Although completely (re)programmable, the  
’ACT715-R/LM1882-R version is better suited for applica-  
tions using the default 14.31818 MHz RS-170 register val-  
ues. This feature allows power-up directly into operation,  
following a single CLEAR pulse.  
General Description  
The ’ACT715/LM1882 and ’ACT715-R/LM1882-R are  
20-pin TTL-input compatible devices capable of generating  
Horizontal, Vertical and Composite Sync and Blank signals  
for televisions and monitors. All pulse widths are completely  
definable by the user. The devices are capable of generat-  
ing signals for both interlaced and noninterlaced modes of  
operation. Equalization and serration pulses can be intro-  
duced into the Composite Sync signal when needed.  
Features  
Y
Y
Y
l
130 MHz  
Maximum Input Clock Frequency  
Four additional signals can also be made available when  
Composite Sync or Blank are used. These signals can be  
used to generate horizontal or vertical gating pulses, cursor  
position or vertical Interrupt signal.  
Interlaced and non-interlaced formats available  
Separate or composite horizontal and vertical Sync and  
Blank signals available  
Y
Complete control of pulse width via register  
programming  
These devices make no assumptions concerning the sys-  
tem architecture. Line rate and field/frame rate are all a  
function of the values programmed into the data registers,  
the status register, and the input clock frequency.  
Y
Y
Y
All inputs are TTL compatible  
8 mA drive on all outputs  
Default RS170/NTSC values mask programmed into  
registers  
The ’ACT715/LM1882 is mask programmed to default to a  
Clock Disable state. Bit 10 of the Status Register, Register  
0, defaults to a logic ‘‘0’’. This facilitates (re)programming  
before operation.  
Y
Y
4 KV minimum ESD immunity  
’ACT715-R/LM1882-R is mask programmed to default  
to a Clock Enable state for easier start-up into  
14.31818 MHz RS170 timing  
The ’ACT715-R/LM1882-R is the same as the  
’ACT715/LM1882 in all respects except that the  
Connection Diagrams  
Pin Assignment for  
DIP and SOIC  
Pin Assignment  
for LCC  
TL/F/10137–1  
Order Number LM1882CN or LM1882CM  
For Default RS-170, Order Number LM1882-RCN or  
LM1882-RCM  
TL/F/10137–2  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
FACTTM is a trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/10137  
RRD-B30M105/Printed in U. S. A.  
1234567...16

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