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LM1882-RD

更新时间： 2024-11-23 15:44:55
品牌 Logo 应用领域
德州仪器 - TI 商用集成电路
页数 文件大小 规格书
19页 383K
描述
SPECIALTY CONSUMER CIRCUIT, CDIP20, CERAMIC, DIP-20

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中文翻译

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LM1882-RD 技术参数

生命周期：Obsolete包装说明：DIP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.65商用集成电路类型：CONSUMER CIRCUIT
JESD-30 代码：R-GDIP-T20长度：24.51 mm
功能数量：1端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
认证状态：Not Qualified座面最大高度：5.08 mm
最大压摆率：1.6 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V表面贴装：NO
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

LM1882-RD 数据手册

 浏览型号LM1882-RD的Datasheet PDF文件第2页浏览型号LM1882-RD的Datasheet PDF文件第3页浏览型号LM1882-RD的Datasheet PDF文件第4页浏览型号LM1882-RD的Datasheet PDF文件第5页浏览型号LM1882-RD的Datasheet PDF文件第6页浏览型号LM1882-RD的Datasheet PDF文件第7页 
December 1998  
LM1882•54ACT715  
LM1882-R•54ACT715-R Programmable Video Sync  
Generator  
LM1882-R is mask programmed to default to a Clock En-  
abled state. Bit 10 of the Status Register defaults to a logic  
General Description  
The ’ACT715/LM1882 and ’ACT715-R/LM1882-R are 20-pin  
“1”. Although completely (re)programmable, the ’ACT715-R/  
TTL-input compatible devices capable of generating Hori-  
LM1882-R version is better suited for applications using the  
zontal, Vertical and Composite Sync and Blank signals for  
default 14.31818 MHz RS-170 register values. This feature  
televisions and monitors. All pulse widths are completely de-  
allows power-up directly into operation, following a single  
finable by the user. The devices are capable of generating  
CLEAR pulse.  
signals for both interlaced and noninterlaced modes of op-  
eration. Equalization and serration pulses can be introduced  
into the Composite Sync signal when needed.  
Features  
>
n Maximum Input Clock Frequency 130 MHz  
Four additional signals can also be made available when  
Composite Sync or Blank are used. These signals can be  
used to generate horizontal or vertical gating pulses, cursor  
position or vertical Interrupt signal.  
n Interlaced and non-interlaced formats available  
n Separate or composite horizontal and vertical Sync and  
Blank signals available  
n Complete control of pulse width via register  
programming  
n All inputs are TTL compatible  
These devices make no assumptions concerning the system  
architecture. Line rate and field/frame rate are all a function  
of the values programmed into the data registers, the status  
register, and the input clock frequency.  
n 8 mA drive on all outputs  
n Default RS170/NTSC values mask programmed into  
registers  
n 4 KV minimum ESD immunity  
n ’ACT715-R/LM1882-R is mask programmed to default to  
a Clock Enable state for easier start-up into  
14.31818 MHz RS170 timing  
The ’ACT715/LM1882 is mask programmed to default to a  
Clock Disable state. Bit 10 of the Status Register, Register 0,  
defaults to a logic “0”. This facilitates (re)programming be-  
fore operation.  
The ’ACT715-R/LM1882-R is the same as the ’ACT715/  
LM1882 in all respects except that the ’ACT715-R/  
Connection Diagrams  
Pin Assignment for  
DIP and SOIC  
Pin Assignment  
for LCC  
DS100232-1  
DS100232-2  
Order Number LM1882CN or LM1882CM  
For Default RS-170, Order Number  
LM1882-RCN or LM1882-RCM  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
™
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 1998 National Semiconductor Corporation  
DS100232  
www.national.com  
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