is possible without interruption or data and performance cor-
ruption. If the defaulted 14.31818 MHz RS-170 values are
being used, preconditioning and restarting can be minimized
by using the CLEAR pulse instead of the Vectored Restart
operation. The ’ACT715-R/LM1882-R is better suited for this
application because it eliminates the need to program a 1
into Bit 10 of the Status Register to enable the CLOCK. Gen
Locking to another count location other than the very begin-
ning or separate horizontal/vertical resetting is not possible
with the ’ACT715/LM1882 nor the ’ACT715-R/LM1882-R.
Addressing Logic (Continued)
Address 19–21Unused
Address 22/54Restart Vector (Restarts Device)
Address 23/55Clear Vector (Zeros All Registers)
Address 24–31Unused
Address 32–50Register Scan Addresses
Address 51–53Counter Scan Addresses
Address 56–63Unused
At any given time only one register at most is selected. It is
possible to have no registers selected.
SCAN MODE LOGIC
A scan mode is available in the ACT715/LM1882 that allows
the user to non-destructively verify the contents of the regis-
ters. Scan mode is invoked through reading a scan address
into the address register. The scan address of a given regis-
ter is defined by the Data register address + 32. The internal
Clocking signal is disabled when a scan address is read.
Disabling the clock freezes the device in it’s present state.
Data can then be serially scanned out of the data registers
through the ODD/EVEN Pin. The LSB will be scanned out
first. Since each register is 12 bits wide, completely scanning
out data of the addressed register will require 12 CLOCK
pulses. More than 12 CLOCK pulses on the same register
will only cause the MSB to repeat on the output.
Re-scanning the same register will require that register to be
reloaded. The value of the two horizontal counters and 1 ver-
tical counter can also be scanned out by using address num-
bers 51–53. Note that before the part will scan out the data,
the LOAD signal must be brought back HIGH.
VECTORED RESTART ADDRESS
The function of addresses 22 (16H) or 54 (36H) are similar to
that of the CLR pin except that the preprogramming of the
registers is not affected. It is recommended but not required
that this address is read after the initial device configuration
load sequence. A 1 on the ADDRDATA pin (Auto Addressing
Mode) will not cause this address to automatically incre-
ment. The address will loop back onto itself regardless of the
state of ADDRDATA unless the address on the Data inputs
has been changed with ADDRDATA at 0.
VECTORED CLEAR ADDRESS
Addresses 23 (17H) or 55 (37H) is used to clear all registers
to zero simultaneously. This function may be desirable to use
prior to loading new data into the Data or Status Registers.
This address is read into the device in a similar fashion as all
of the other registers. A 1 on the ADDRDATA pin (Auto Ad-
dressing Mode) will not cause this address to automatically
increment. The address will loop back onto itself regardless
of the state of ADDRDATA unless the address on the Data
inputs has been changed with ADDRDATA at 0.
Normal device operation can be resumed by loading in a
non-scan address. As the scanning of the registers is a
non-destructive scan, the device will resume correct opera-
tion from the point at which it was halted.
RS170 Default Register Values
The tables below show the values programmed for the
RS170 Format (using a 14.31818 MHz clock signal) and
how they compare against the actual EIA RS170 Specifica-
tions. The default signals that will be output are CSYNC,
CBLANK, HDRIVE and VDRIVE. The device initially starts at
the beginning of the odd field of interlace. All signals have
active low pulses and the clock is disabled at power up. Reg-
isters 13 and 14 are not involved in the actual signal informa-
tion. If the Vertical Interrupt was selected so that a pulse in-
dicating the active lines would be output.
DS100232-9
FIGURE 4. ADDRDEC Timing
GEN LOCKING
The ’ACT715/LM1882 and ’ACT715-R/LM1882-R is de-
signed for master SYNC and BLANK signal generation.
However, the devices can be synchronized (slaved) to an ex-
ternal timing signal in a limited sense. Using Vectored Re-
start, the user can reset the counting sequence to a given lo-
cation, the beginning, at a given time, the rising edge of the
LOAD that removes Vector Restart. At this time the next
CLOCK pulse will be CLOCK 1 and the count will restart at
the beginning of the first odd line.
Preconditioning the part during normal operation, before the
desired synchronizing pulse, is necesasry. However, since
LOAD and CLOCK are asynchronous and independent, this
7
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