Datasheet > 存储 > MASK ROM> LH532100B

LH532100B

更新时间： 2024-11-08 22:33:07

品牌	Logo	应用领域
夏普 - SHARP		/
页数	文件大小	规格书
8页	82K
描述
CMOS 2M (256K x 8) MROM

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中文翻译

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LH532100B 数据手册

LH532100B

CMOS 2M (256K × 8) MROM

FEATURES

DESCRIPTION

The LH532100B is a 2M-bit mask-programmable

ROM organized as 262,144 × 8 bits. It is fabricated

using silicon-gate CMOS process technology.

• 262,144 words × 8 bit organization

• Access time: 150 ns (MAX.)

• Low-power consumption:

Operating: 275 mW (MAX.)

Standby: 550 µW (MAX.)

PIN CONNECTIONS

32-PIN DIP

32-PIN SOP

TOP VIEW

OE₁/OE₁/DC

V_CC

• Static operation

A₁₆

A₁₅

A₁₂

30 A₁₇

29 A₁₄

• Mask-programmable OE/OE and

OE₁/OE₁/DC

A₁₃

27 A₈

A₇

A₆

A₅

A₄

A₃

A₂

A₁

A₀

• TTL compatible I/O

A₉

A₁₁

• Three-state outputs

• Single +5 V power supply

24 OE/OE

A₁₀

D₇

D₆

D₅

D₄

D₃

• Packages:

D₀13

D₁14

32-pin, 600-mil DIP

32-pin, 525-mil SOP

32-pin, 450-mil QFJ (PLCC)

32-pin, 8 × 20 mm²TSOP (Type I)

32-pin, 400-mil TSOP (Type II)

D₂15

GND 16

532100B-1

Figure 1. Pin Connections for DIP and

SOP Packages

• JEDEC standard EPROM pinout (DIP)

32-PIN QFJ

TOP VIEW

20 19 18 17 16 15 14

D₇

D₀

A₀

A₁

A₁₀

OE/OE

A₁₁

A₂

A₃

A₄

A₅

A₆

A₇

A₉

A₈

A₁₃

A₁₄

30 31 32

532100B-7

Figure 2. Pin Connections QFJ

(PLCC) Package

12 3 4 5 6 7 8

中文翻译

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与LH532100B相关器件

型号	品牌	获取价格	描述	数据表
LH532100B-1	SHARP	获取价格	CMOS 2M (256K x 8) MROM
LH532100BD	ETC	获取价格	x8 ROM (Mask Programmable)
LH532100BD-1	ETC	获取价格	x8 ROM (Mask Programmable)
LH532100BN	ETC	获取价格	x8 ROM (Mask Programmable)
LH532100BN-1	ETC	获取价格	x8 ROM (Mask Programmable)
LH532100BS	ETC	获取价格	x8 ROM (Mask Programmable)
LH532100BS-1	ETC	获取价格	x8 ROM (Mask Programmable)
LH532100BSR	ETC	获取价格	x8 ROM (Mask Programmable)
LH532100BSR-1	ETC	获取价格	x8 ROM (Mask Programmable)
LH532100BT	ETC	获取价格	x8 ROM (Mask Programmable)