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LC4128B-10T128I

更新时间： 2024-11-25 02:56:19
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莱迪思 - LATTICE 可编程逻辑器件
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74页 487K
描述
3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs

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LC4128B-10T128I 数据手册

 浏览型号LC4128B-10T128I的Datasheet PDF文件第2页浏览型号LC4128B-10T128I的Datasheet PDF文件第3页浏览型号LC4128B-10T128I的Datasheet PDF文件第4页浏览型号LC4128B-10T128I的Datasheet PDF文件第5页浏览型号LC4128B-10T128I的Datasheet PDF文件第6页浏览型号LC4128B-10T128I的Datasheet PDF文件第7页 
TM  
ispMACH 4000V/B/C/Z Family  
3.3V/2.5V/1.8V In-System Programmable  
TM  
SuperFAST High Density PLDs  
July 2003  
Data Sheet  
■ Broad Device Offering  
Features  
• Multiple temperature range support  
■ High Performance  
– Commercial: 0 to 90°C junction (T )  
– Industrial: -40 to 105°C junction (T )  
– Automotive: -40 to 130°C junction (T )  
j
• f  
= 400MHz maximum operating frequency  
MAX  
j
• t = 2.5ns propagation delay  
PD  
j
• Up to four global clock pins with programmable  
clock polarity control  
• Up to 80 PTs per output  
■ Easy System Integration  
• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O  
• Operation with 3.3V (4000V), 2.5V (4000B) or  
1.8V (4000C/Z) supplies  
■ Ease of Design  
• Enhanced macrocells with individual clock,  
reset, preset and clock enable controls  
• Up to four global OE controls  
• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI  
interfaces  
• Hot-socketing  
• Individual local OE control per I/O pin  
• Excellent First-Time-FitTM and refit  
• Fast path, SpeedLockingTM Path, and wide-PT  
path  
• Wide input gating (36 input logic blocks) for fast  
counters, state machines and address decoders  
• Open-drain capability  
• Input pull-up, pull-down or bus-keeper  
• Programmable output slew rate  
• 3.3V PCI compatible  
• IEEE 1149.1 boundary scan testable  
• 3.3V/2.5V/1.8V In-System Programmable  
(ISP™) using IEEE 1532 compliant interface  
• I/O pins with fast setup path  
■ Zero Power (ispMACH 4000Z) and Low  
Power (ispMACH 4000V/B/C)  
• Typical static current 10µA (4032Z)  
• Typical static current 1.8mA (4000C)  
• 1.8V core low dynamic power  
Table 1. ispMACH 4000V/B/C Family Selection Guide  
ispMACH  
4032V/B/C  
ispMACH  
4064V/B/C  
ispMACH  
4128V/B/C  
ispMACH  
4256V/B/C  
ispMACH  
4384V/B/C  
ispMACH  
4512V/B/C  
Macrocells  
32  
30/32  
2.5  
64  
30/32/64  
2.5  
128  
64/92/96  
2.7  
256  
64/96/128/160  
3.0  
384  
128/192  
3.5  
512  
128/208  
3.5  
User I/O Options  
t
(ns)  
PD  
t (ns)  
1.8  
1.8  
1.8  
2.0  
2.0  
2.0  
S
t
f
(ns)  
2.2  
2.2  
2.7  
2.7  
2.7  
2.7  
CO  
(MHz)  
400  
400  
333  
322  
322  
322  
MAX  
Supply Voltages (V)  
Pins/Package  
3.3/2.5/1.8V  
3.3/2.5/1.8V  
3.3/2.5/1.8V  
3.3/2.5/1.8V  
3.3/2.5/1.8V  
3.3/2.5/1.8V  
44 TQFP  
48 TQFP  
44 TQFP  
48 TQFP  
100 TQFP  
100 TQFP  
128 TQFP  
144 TQFP1  
100 TQFP  
144 TQFP1  
176 TQFP  
256 fpBGA2  
176 TQFP  
256 fpBGA  
176 TQFP  
256 fpBGA  
1. 3.3V (4000V) only.  
2. 128-I/O and 160-I/O configurations.  
Note: ispMACH 4032Z information is preliminary. ispMACH 4064Z/4128Z information is advance.  
© 2003 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand  
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.  
www.latticesemi.com  
1
ispm4k_15z  
1234567...74

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