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L9D112G80BG4I75 PDF预览

L9D112G80BG4I75

更新时间: 2024-02-15 01:00:11
品牌 Logo 应用领域
逻辑 - LOGIC 内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
45页 6016K
描述
1.2 Gb, DDR - SDRAM Integrated Module

L9D112G80BG4I75 技术参数

是否Rohs认证:符合生命周期:Contact Manufacturer
零件包装代码:DMA包装说明:BGA, BGA219,16X16,50
针数:219Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.24
风险等级:5.69Is Samacsys:N
访问模式:FOUR BANK PAGE BURST最长访问时间:0.75 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMON交错的突发长度:2,4,8
JESD-30 代码:S-XDMA-N219长度:25 mm
内存密度:268435456 bit内存集成电路类型:DDR DRAM MODULE
内存宽度:16功能数量:1
端口数量:1端子数量:219
字数:16777216 words字数代码:16000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:16MX16
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:BGA封装等效代码:BGA219,16X16,50
封装形状:SQUARE封装形式:MICROELECTRONIC ASSEMBLY
电源:2.5 V认证状态:Not Qualified
刷新周期:8192座面最大高度:2.5 mm
自我刷新:YES连续突发长度:2,4,8
最大待机电流:0.025 A子类别:DRAMs
最大压摆率:1.92 mA最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子形式:NO LEAD
端子节距:1.27 mm端子位置:DUAL
宽度:25 mmBase Number Matches:1

L9D112G80BG4I75 数据手册

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PreLIMINArY INforMAtIoN L9D112G80BG4  
1.2 Gb, DDR - SDRAM Integrated Module (IMOD)  
Benefits  
FEATURES  
53% SPACE savings vs. Monolithic,  
TSOPII-66 solution  
DDR SDRAM Data Rate = 200, 250,  
266, and 333 Mbps  
DQS edge-aligned with data for  
READ; center-aligned with data for  
WRITE  
Reduced I/O routing (34%)  
Package:  
DLL to align DQx and DQSLx,  
DQSHx transitions with CLKx  
Reduced trace length providing  
improved/reduced parasitic capaci-  
tance  
• 25mm x 25mm, Encapsulated  
Plastic Ball Grid array (PBGA), 219  
balls, 1.27mm pitch.  
Four internal banks for concurrent  
operation  
Impedance matched (60ohm) pack-  
2.5V ±0.2V Core Power supply  
aging  
One data mask per byte, IMOD con-  
tains (10) bytes  
2.5V ±0.2V I/O Power supply  
(SSTL_2 compatible)  
High TCE organic laminate inter-  
poser  
Programmable IOL/IOH Option  
Auto PRECHARGE option  
Differential Clock inputs (CLKx,  
CLKx\)  
Suitable for High Reliability applica-  
tions  
Commands entered on each positive  
CLKx edge  
Auto REFRESH and SELF  
REFRESH Modes  
Upgradable to 32M x 72/80:  
L9D125G80BG4  
Internal pipelined double-data-  
rate (DDR) Architecture; two data  
accesses per clock cycle  
Available in INDUSTRIAL,  
EXTENDED and Mil-Temp ranges  
Organized as 16M x 72/80  
Programmable Burst Length:  
2, 4, or 8  
Weight: LOGIC Devices, Inc.  
L9D112G80BG4 = 2.75 grams  
Bidirectional data strobe (DQSLx,  
DQsHx) per byte transmitted/  
received with data  
typical  
i.e. source-synchronous data capture  
*Note: This integrated product and/or its specifications are subject to change without notice.  
Latest document should be retrieved from LDI prior to your design consideration.  
IMOD SOLUTION  
MONOLITHIC SOLUTION  
S
A
V
I
N
G
S
O
P
T
I
O
N
S
11.9  
11.9  
11.9  
11.9  
11.9  
25mm  
22.3  
25mm  
625mmꢀ  
53%  
34%  
AREA  
I/O  
5 X 265mmꢀ = 1328mmꢀ PLUS  
5 X 66 pins = 320 pins total  
219 Balls/Locations  
LOGIC Devices Incorporated  
www.logicdevices.com  
High Performance, Integrated Memory Module Product  
1
Feb 2, 2009 LDS-L9D112G80BG4-C  

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