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KSZ8895MLU-EVAL

更新时间： 2024-09-15 22:56:51
品牌 Logo 应用领域
美国微芯 - MICROCHIP 局域网（LAN）标准
页数 文件大小 规格书
117页 1858K
描述
EVALUATION BOARD 5-PORT 10/100 S

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KSZ8895MLU-EVAL 数据手册

 浏览型号KSZ8895MLU-EVAL的Datasheet PDF文件第2页浏览型号KSZ8895MLU-EVAL的Datasheet PDF文件第3页浏览型号KSZ8895MLU-EVAL的Datasheet PDF文件第4页浏览型号KSZ8895MLU-EVAL的Datasheet PDF文件第5页浏览型号KSZ8895MLU-EVAL的Datasheet PDF文件第6页浏览型号KSZ8895MLU-EVAL的Datasheet PDF文件第7页 
KSZ8895MLU  
Integrated 5-Port 10/100 Managed Switch  
Revision 1.2  
General Description  
The KSZ8895MLU is a highly-integrated Layer 2-  
managed 5-port switch with an optimized design and  
plentiful features, qualified to meet AEC-Q100 standard  
for automotive applications. It is designed for cost-  
sensitive 10/100Mbps 5-port switch systems with on-chip  
termination, lowest power consumption and internal core  
power controller. These features will save more system  
cost. It has 1.4Gbps high-performance memory  
bandwidth, shared memory based switch fabric with full  
non-blocking configuration. It also provides an extensive  
feature set such as power management, programmable  
rate limit and priority ratio, tag/port-based VLAN, packets  
The KSZ8895MLU consists of 10/100 PHYs with  
patented and enhanced mixed-signal technology, media  
access control (MAC) units, a high-speed non-blocking  
switch fabric, a dedicated address lookup engine, and an  
on-chip frame buffer memory. The KSZ8895MLU  
contains five MACs and four integrated PHYs. All PHYs  
support 10/100Base-T/TX.  
All registers of MACs and PHYs units can be managed  
by the SPI interface or the SMI interface. MIIM registers  
of the PHYs can be accessed through the MDC/MDIO  
interface. EEPROM can set all control registers for the  
unmanaged mode.  
filtering,  
quality-of-service  
(QoS)  
four-queue  
The KSZ8895MLU provides multiple CPU control/data  
interfaces to effectively address both current and  
emerging fast Ethernet applications.  
prioritization, management interface, and MIB counters.  
Port 5 is a MAC 5 MII interface with PHY mode as  
default at switch side. The SW5-MII interface can be  
connected to a processor with a MAC MII interface.  
Datasheets and support documentation are available on  
Micrel’s web site at: www.micrel.com.  
Functional Diagram  
KSZ8895MLU  
10/100  
T/Tx 1  
PHY1  
10/100  
1K LookUp  
Auto MDI/MDIX  
MAC 1  
Engine  
10/100  
T/Tx 2  
PHY2  
10/100  
MAC 2  
Auto MDI/MDIX  
Auto MDI/MDIX  
Queue  
Mgmnt  
10/100  
MAC 3  
10/100  
T/Tx 3  
PHY3  
Buffer  
10/100  
T/Tx 4  
PHY4  
10/100  
Mgmnt  
Auto MDI/MDIX  
MAC 4  
10/100  
Frame  
MAC 5  
Buffers  
SW5-MII  
MDC,MDI/O for MIIM and SMI  
SNI  
SNI  
MIB  
Control Reg SPI I/F  
SPI  
Counters  
LED0[5:1]  
LED1[5:1]  
LED2[5:1]  
EEPROM  
I/F  
Control  
Registers  
LED I/F  
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com  
Revision 1.2  
April 28, 2014  
1234567...117

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