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KSZ8842-32MVL PDF预览

KSZ8842-32MVL

更新时间: 2024-11-14 03:48:51
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麦瑞 - MICREL PC以太网
页数 文件大小 规格书
126页 2948K
描述
2-Port Ethernet Switch with Non-PCI Interface

KSZ8842-32MVL 数据手册

 浏览型号KSZ8842-32MVL的Datasheet PDF文件第2页浏览型号KSZ8842-32MVL的Datasheet PDF文件第3页浏览型号KSZ8842-32MVL的Datasheet PDF文件第4页浏览型号KSZ8842-32MVL的Datasheet PDF文件第5页浏览型号KSZ8842-32MVL的Datasheet PDF文件第6页浏览型号KSZ8842-32MVL的Datasheet PDF文件第7页 
KSZ8842-16/32  
MQL/MVL/MVLI  
2-Port Ethernet Switch with Non-PCI Interface  
Data Sheet Rev 1.4  
General Description  
The KSZ8842-series of 2-port switches includes PCI and  
non-PCI CPU interfaces, and are available in 8/16-bit  
and 32-bit bus designs (see Ordering Information).  
This datasheet describes the KSZ8842M-series of non-  
PCI CPU interface chips. For information on the  
KSZ8842 PCI CPU interface switches, refer to the  
KSZ8842P datasheet.  
The KSZ8842M offers an extensive feature set that  
includes tag/port-based VLAN, quality of service (QoS)  
priority management, management information base  
(MIB) counters, and CPU control/data interfaces to  
effectively address Fast Ethernet applications.  
The KSZ8842M contains: Two 10/100 transceivers with  
patented, mixed-signal, low-power technology, two  
media access control (MAC) units, a direct memory  
access (DMA) channel, a high-speed, non-blocking,  
switch fabric, a dedicated 1K entry forwarding table, and  
an on-chip frame buffer memory.  
The KSZ8842M is the industry’s first fully managed, 2-  
port switch with a non-PCI CPU interface. It is based on  
a proven, 4th generation, integrated Layer-2 switch,  
compliant with IEEE 802.3u standards. Also an industrial  
temperature grade version of the KSZ8842, the  
KSZ8842MQLI, can be ordered (see Ordering  
Information).  
The KSZ8842M can be configured as a switch or as a  
low-latency (310 nanoseconds) repeater in latency-  
critical, embedded or industrial Ethernet applications.  
For industrial applications, the KSZ8842M can run in  
half-duplex mode regardless of the application.  
Functional Diagram  
1 K lo o k -u p  
E n g in e  
P 1 H P A u to  
M D I/M D I-X  
1 0 /1 0 0 B a s e -  
T /T X  
1 0 /1 0 0  
M A C  
1
P H Y  
1
S c h e d u lin g  
M a n a g e m e n t  
P 2 H P A u to  
M D I/M D I-X  
1 0 /1 0 0 B a s e -  
T /T X  
1 0 /1 0 0  
M A C  
2
P H Y  
2
B u ffe r  
M a n a g e m e n t  
R X Q  
4 K B  
Q M U  
D M A  
C h a n n e l  
S w itc h  
H o s t  
N o n -P C I  
C P U  
M A C  
T X Q  
4 K B  
d e d  
E m b e d  
P ro c e s  
B u s  
In te rfa c e  
U n it  
rfa c e  
F ra m e  
B u ffe rs  
s o r In te  
C o n tro l  
R e g is te rs  
8 ,1 6 , o r 3 2 -b it  
G e n e ric H o s t  
In te rfa c e  
M IB  
C o u n te rs  
P 1 L E D [3 :0 ]  
P 2 L E D [3 :0 ]  
L E D  
D riv e rs  
E E P R O M  
In te rfa c e  
E E P R O M I/F  
Figure 1. KSZ8842M Functional Diagram  
November 2005  
1
Rev. 1.4  
 

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