KSZ8851-16/32MQL
Single-Port Ethernet MAC Controller
with 8/16-Bit or 32-Bit Non-PCI Interface
•
Features
• Flexible Package Options Available in 128-pin
PQFP: KSZ8851-16/32MQL or 48-pin LQFP
KSZ8851-16MLL
• Pin Compatible with Existing 128-pin KSZ8841-16/
32MQL and KSZ8842-16/32MQL
• Integrated MAC and PHY Ethernet Controller Fully
Compliant with IEEE 802.3/802.3u Standards
• Designed for High Performance and High Through-
put Applications
• Supports 10BASE-T/100BASE-TX
• Supports IEEE 802.3x Full-Duplex Flow Control and
Half-Duplex Backpressure Collision Flow Control
• Supports DMA-Slave Burst Data Read and Write
Transfers
• Supports IP Header (IPv4)/TCP/UDP/ICMP Check-
sum Generation and Checking
• Supports IPv6 TCP/UDP/ICMP Checksum Genera-
tion and Checking
Additional Features
In addition to offering all of the features of a Layer 2 con-
troller, the KSZ8851-16/23MQL offers:
• Flexible 8-bit, 16-bit, and 32-bit Generic Host Pro-
cessor Interfaces with Same Access Time and Sin-
gle Bus Timing to Any I/O Registers and RX/TX FIFO
Buffers
• Supports Adding Two-Bytes Before Frame Header in
Order for IP Frame Content with Double Word
Boundary
• Automatic 32-bit CRC Generation and Checking
• Simple SRAM-Like Host Interface Easily Connects to
Most Common Embedded MCUs
®
• LinkMD Cable Diagnostic Capabilities to Determine
• Supports Multiple Data Frames for Transmit and
Receive without Address Bus and Byte-Enable Sig-
nals
Cable Length, Diagnose Faulty Cables, and Deter-
mine Distance to Fault
• Wake-on-LAN Functionality
• Supports Both Big- and Little-Endian Processors
• Larger Internal Memory with 12K Bytes for RX FIFO
and 6K Bytes for TX FIFO. Programmable Low,
High, and Overrun Watermark for Flow Control in RX
FIFO
• Efficient Architecture Design with Configurable Host
Interrupt Schemes to Minimize Host CPU Overhead
and Utilization
• Powerful and Flexible Address Filtering Scheme
• Optional to Use External Serial EEPROM Configura-
tion for Both KSZ8851-16MQL and KSZ8851-
32MQL
• Single 25 MHz Reference Clock for Both PHY and
MAC
- Incorporates Magic Packet™, Network Link
State, and Wake-Up Frame Technology
• HP Auto MDI-X™ Crossover with Disable/Enable
Option
• Ability to Transmit and Receive Frames up to 2000
Bytes
Network Features
• 10BASE-T and 100BASE-TX Physical Layer Sup-
port
• Auto-Negotiation: 10/100 Mbps Full- and Half-
Duplex
• Adaptive Equalizer
• Baseline Wander Correction
Power Modes, Power Supplies, and
Packaging
• Single 3.3V Power Supply with Options for 1.8V,
2.5V, and 3.3V VDD I/O
• Built-In Integrated 3.3V or 2.5V to 1.8V Low Noise
Regulator (LDO) for Core and Analog Blocks
• Enhanced Power Management Feature with Energy
Detect Mode and Power-Down Mode to Ensure Low-
Power Dissipation During Device Idle Periods
• Comprehensive LED Indicator Support for Link,
Activity and 10/100 Speed (2 LEDs)
Applications
• Video/Audio Distribution Systems
• High-End Cable, Satellite, and IP Set-Top Boxes
• Video over IP and IPTV
• Voice over IP (VoIP) and Analog Telephone Adapters
(ATA)
• Industrial Control in Latency-Critical Applications
• Home Base Station with Ethernet Connection
• Industrial Control Sensor Devices (Temp., Pressure,
Levels, and Valves)
• Security, Motion Control, and Surveillance Cameras
- User Programmable
• Low-Power CMOS Design
• Commercial Temperature Range: 0°C to +70°C
• Industrial Temperature Range: –40°C to +85°C
Markets
• Fast Ethernet
• Embedded Ethernet
• Industrial Ethernet
• Embedded Systems
2017 Microchip Technology Inc.
DS00002425A-page 1