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KSZ8851 PDF预览

KSZ8851

更新时间: 2024-11-15 14:54:39
品牌 Logo 应用领域
美国微芯 - MICROCHIP PC
页数 文件大小 规格书
86页 1699K
描述
The KSZ8851 is a single-port controller chip with a SPI or 8-/16-/32-bit non-PCI CPU interface.

KSZ8851 数据手册

 浏览型号KSZ8851的Datasheet PDF文件第2页浏览型号KSZ8851的Datasheet PDF文件第3页浏览型号KSZ8851的Datasheet PDF文件第4页浏览型号KSZ8851的Datasheet PDF文件第5页浏览型号KSZ8851的Datasheet PDF文件第6页浏览型号KSZ8851的Datasheet PDF文件第7页 
KSZ8851-16MLL/MLLI/MLLU  
Single-Port Ethernet MAC Controller with 8-Bit  
or 16-Bit Non-PCI Interface  
Highlights  
Features  
• Single-Port Controller Chip with Non-PCI CPU  
Interface  
• Integrated MAC and PHY Ethernet Controller  
Fully Compliant with IEEE 802.3/802.3u  
Standards  
• Mixed Analog/Digital Device Offering Wake-On-  
LAN Technology for Effectively Addressing Fast  
Ethernet Applications  
• Designed for High Performance and High  
Throughput Applications  
• HP Auto-MDIX Support  
• Supports 10BASE-T/100BASE-TX  
• Supports IEEE 802.3x Full-Duplex Flow Control  
and Half-Duplex Backpressure Collision Flow  
Control  
Target Applications  
• Video/Audio Distribution Systems  
• High-End Cable, Satellite, and IP Set-Top Boxes  
• Video over IP and IPTV  
• Supports DMA-Slave Burst Data Read and Write  
Transfers  
• Supports IP Header (IPv4)/TCP/UDP/ICMP  
Checksum Generation and Checking  
• Voice over IP (VoIP) and Analog Telephone  
Adapters (ATA)  
• Supports IPv6 TCP/UDP/ICMP Checksum   
Generation and Checking  
• Industrial Control in Latency Critical Applications  
• Home Base Station with Ethernet Connection  
• Automatic 32-Bit CRC Generation and Checking  
• Industrial Control Sensor Devices (Temperature,  
Pressure, Levels, and Valves)  
• Simple SRAM-like Host Interface Easily Connects  
to Most Common Embedded MCUS  
• Security, Motion Control and Surveillance   
Cameras  
• Supports Multiple Data Frames for Receive with-  
out Address Bus and Byte-Enable Signals  
• In-Vehicle Diagnostics (OBD) and Software  
Download  
• Supports Both Big- and Little-Endian Processors  
• Larger Internal Memory with 12 kb for RX FIFO  
and 6 kb for TX FIFO. Programmable Low, High  
and Overrun Watermark for Flow Control in Rx  
FIFO  
• Shared Data Bus for Data, Address, and Byte  
Enable  
• Efficient Architecture Design with Configurable  
Host Interrupt Schemes to Minimize Host CPU  
Overhead and Utilization  
• Powerful and Flexible Address Filtering Scheme  
• Optional to Use External Serial EEPROM Config-  
uration for MAC Address  
• Single 25 MHz Reference Clock for Both PHY  
and MAC  
• HBM ESD Rating 6 kV  
2018 Microchip Technology Inc.  
DS00002357B-page 1  

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