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KS32C50100Q PDF预览

KS32C50100Q

更新时间: 2024-02-05 13:12:27
品牌 Logo 应用领域
三星 - SAMSUNG 时钟微控制器外围集成电路
页数 文件大小 规格书
26页 185K
描述
RISC Microcontroller, CMOS, PQFP208, QFP-208

KS32C50100Q 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:QFP,针数:208
Reach Compliance Code:unknownECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.84
具有ADC:NO地址总线宽度:22
最大时钟频率:50 MHzDAC 通道:NO
DMA 通道:YES外部数据总线宽度:32
JESD-30 代码:S-PQFP-G208I/O 线路数量:18
端子数量:208最高工作温度:70 °C
最低工作温度:PWM 通道:NO
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:SQUARE封装形式:FLATPACK
认证状态:Not Qualified最大供电电压:3.63 V
最小供电电压:2.97 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子位置:QUADuPs/uCs/外围集成电路类型:MICROCONTROLLER, RISC
Base Number Matches:1

KS32C50100Q 数据手册

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KS32C50100 RISC MICROCONTROLLER  
PRODUCT OVERVIEW  
1
PRODUCT OVERVIEW  
OVERVIEW  
Samsung's KS32C50100 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller  
solution for Ethernet-based systems. An integrated Ethernet controller, the KS32C50100, is designed for use in  
managed communication hubs and routers.  
The KS32C50100 is built around an outstanding CPU core: the 16/32-bit ARM7TDMI RISC processor designed by  
Advanced RISC Machines, Ltd. The ARM7TDMI core is a low-power, general purpose microprocessor macro-cell  
that was developed for use in application-specific and custom-specific integrated circuits. Its simple, elegant, and  
fully static design is particularly suitable for cost-sensitive and power-sensitive applications.  
The KS32C50100 offers a configurable 8-Kbyte unified cache/SRAM and Ethernet controller which reduces total  
system cost. Most of the on-chip function blocks have been designed using an HDL synthesizer and the  
KS32C50100 has been fully verified in Samsung's state-of-the-art ASIC test environment.  
Important peripheral functions include two HDLC channels with buffer descriptor, two UART channels, 2-channel  
GDMA, two 32-bit timers, and 18 programmable I/O ports. On-board logic includes an interrupt controller, DRAM/  
SDRAM controller, and a controller for ROM/SRAM and flash memory. The System Manager includes an internal  
32-bit system bus arbiter and an external memory controller.  
The following integrated on-chip functions are described in detail in this user's manual:  
8-Kbyte unified cache/SRAM  
I2C interface  
Ethernet controller  
HDLC  
GDMA  
UART  
Timers  
Programmable I/O ports  
Interrupt controller  
1-1  

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