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KM681000BLRE-7L PDF预览

KM681000BLRE-7L

更新时间: 2024-11-04 22:27:47
品牌 Logo 应用领域
三星 - SAMSUNG /
页数 文件大小 规格书
11页 195K
描述
128K x8 bit Low Power CMOS Static RAM

KM681000BLRE-7L 数据手册

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PRELIMINARY  
KM681000B Family  
CMOS SRAM  
128K x8 bit Low Power CMOS Static RAM  
FEATURES  
GENERAL DESCRIPTION  
The KM681000B family is fabricated by SAMSUNG's advanced  
CMOS process technology. The family can support various  
operating temperature ranges and have various package types  
for user flexibility of system design. The family also support low  
data retention voltage for battery back-up operation with low  
data retention current.  
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§•  
Process Technology : 0.6  
Organization : 128Kx8  
CMOS  
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¡ ¾  
Power Supply Voltage : Single 5.0V  
Low Data Retention Voltage : 2V(Min)  
Three state output and TTL Compatible  
Package Type : JEDEC Standard  
10%  
32-DIP, 32-SOP, 32-TSOP I R/F  
PRODUCT FAMILY  
Power Dissipation  
PKG Type  
Product  
Family  
Operating  
Temperature  
Speed  
Standby  
Operating  
(ICC2)  
(ISB1, Max)  
KM681000BL  
KM681000BL-L  
KM681000BLE  
§Ë  
100  
32-DIP,32-SOP  
32-TSOP I R/F  
¡ É  
Commercial(0~7  
)
55/70ns  
70/100ns  
70/100ns  
§Ë  
20  
§Ë  
100  
32-SOP  
32-TSOP I R/F  
¡ É  
Extended(-25~85  
)
70mA  
KM681000BLE-L  
KM681000BLI  
§Ë  
50  
§Ë  
100  
32-SOP  
32-TSOP I R/F  
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)
Industrial(-40~85  
KM681000BLI-L  
§Ë  
50  
PIN DESCRIPTION  
FUNCTIONAL BLOCK DIAGRAM  
A0~3, A8~11  
A11  
1
32  
31  
30  
29  
28  
27  
26  
25  
24  
OE  
A10  
Y-Decoder  
A9  
A8  
2
3
CS1  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
VSS  
I/O3  
I/O2  
I/O1  
A0  
A13  
WE  
CS2  
A15  
VCC  
NC  
A16  
A14  
A12  
A7  
4
5
6
VCC  
A15  
N.C  
A16  
A14  
A12  
A7  
1
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
7
2
8
32-TSOP  
Type I - Forward  
9
CS2  
WE  
A13  
A4~7,  
A12~16  
3
10  
11  
12  
13  
14  
15  
16  
23  
22  
21  
20  
19  
18  
17  
4
Cell  
Array  
5
CS1,CS2  
A6  
A1  
A8  
A6  
6
A5  
A2  
WE,OE  
A9  
A5  
7
A4  
32-DIP  
32-SOP  
A3  
A11  
A4  
8
I/O1~8  
OE  
A10  
A3  
9
I/O Buffer  
A2  
10  
11  
12  
13  
14  
15  
16  
16  
15  
14  
13  
12  
11  
10  
9
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
A3  
A4  
A5  
CS1  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
A1  
A2  
A1  
A6  
A0  
A0  
A7  
I/O1  
I/O2  
I/O3  
VSS  
I/O4  
I/O5  
I/O6  
I/O7  
I/O8  
CS1  
A10  
A12  
A14  
A16  
NC  
VCC  
A15  
CS2  
WE  
A13  
A8  
/O1  
/O2  
/O3  
VSS  
Name  
A0~A16  
WE  
Function  
32-TSOP  
Type I-Reverse  
Address Inputs  
Write Enable Input  
Chip Select Inputs  
Output Enable Input  
Data Inputs/Outputs  
Power  
8
7
6
5
CS1,CS2  
OE  
4
3
2
A9  
1
A11  
OE  
I/O1~I/O18  
Vcc  
Vss  
Ground  
N.C  
No Connection  
Revision 0.3  
April 1996  

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