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KM48V8104BS-L45 PDF预览

KM48V8104BS-L45

更新时间: 2024-11-03 14:43:03
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
21页 386K
描述
EDO DRAM, 8MX8, 45ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32

KM48V8104BS-L45 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2, TSOP32,.46
针数:32Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.92访问模式:FAST PAGE WITH EDO
最长访问时间:45 ns其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN/SELF REFRESH
I/O 类型:COMMONJESD-30 代码:R-PDSO-G32
JESD-609代码:e0长度:20.95 mm
内存密度:67108864 bit内存集成电路类型:EDO DRAM
内存宽度:8功能数量:1
端口数量:1端子数量:32
字数:8388608 words字数代码:8000000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8MX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP32,.46
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified刷新周期:4096
座面最大高度:1.2 mm自我刷新:YES
最大待机电流:0.0003 A子类别:DRAMs
最大压摆率:0.13 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10.16 mmBase Number Matches:1

KM48V8104BS-L45 数据手册

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KM48V8004B,KM48V8104B  
CMOS DRAM  
8M x 8bit CMOS Dynamic RAM with Extended Data Out  
DESCRIPTION  
This is a family of 8,388,608 x 8 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random  
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5 or -6), power consumption(Normal  
or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh  
capabilities. Furthermore, Self-refresh operation is available in L-version. This 8Mx8 EDO Mode DRAM family is fabricated using Sam-  
sung¢s advanced CMOS process to realize high band-width, low power consumption and high reliability.  
• Extended Data Out Mode operation  
FEATURES  
• CAS-before-RAS refresh capability  
• Part Identification  
• RAS-only and Hidden refresh capability  
• Self-refresh capability (L-ver only)  
• Fast parallel test mode capability  
• LVTTL(3.3V) compatible inputs and outputs  
• Early Write or output enable controlled write  
• JEDEC Standard pinout  
- KM48V8004B/B-L(3.3V, 8K Ref.)  
- KM48V8104B/B-L(3.3V, 4K Ref.)  
Active Power Dissipation  
Unit : mW  
Speed  
-45  
-5  
8K  
4K  
• Available in Plastic SOJ and TSOP(II) packages  
• +3.3V±0.3V power supply  
360  
324  
288  
468  
432  
396  
-6  
Refresh Cycles  
FUNCTIONAL BLOCK DIAGRAM  
Part  
NO.  
Refresh  
cycle  
Refresh time  
Normal  
L-ver  
RAS  
CAS  
W
Vcc  
Vss  
Control  
Clocks  
KM48V8004B*  
KM48V8104B  
8K  
4K  
64ms  
128ms  
VBB Generator  
* Access mode & RAS only refresh mode  
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)  
CAS-before-RAS & Hidden refresh mode  
Row Decoder  
Refresh Timer  
Refresh Control  
Data in  
Buffer  
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)  
Memory Array  
8,388,608 x 8  
Cells  
DQ0  
to  
DQ7  
Refresh Counter  
Row Address Buffer  
Col. Address Buffer  
¡ Ü  
Performance Range:  
Data out  
Buffer  
A0~A12  
(A0~A11)*1  
Speed  
-45  
-5  
tRAC  
45ns  
50ns  
60ns  
tCAC  
12ns  
13ns  
15ns  
tRC  
tHPC  
17ns  
20ns  
25ns  
OE  
74ns  
84ns  
104ns  
A0~A9  
(A0~A10)*1  
Column Decoder  
Note) *1 : 4K Refresh  
-6  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  

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