Datasheet > KM48C8104CK-5

KM48C8104CK-5

更新时间： 2024-11-02 09:20:31

品牌	Logo	应用领域
三星 - SAMSUNG		动态存储器光电二极管
页数	文件大小	规格书
21页	445K
描述
EDO DRAM, 8MX8, 50ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

KM48C8104CK-5 数据手册

KM48C8004C,KM48C8104C

CMOS DRAM

8M x 8bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

This is a family of 8,388,608 x 8 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random

access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-5 or -6), package type (SOJ or TSOP-II)

are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities.

This 8Mx8 EDO Mode DRAM family is fabricated using Samsung¢s advanced CMOS process to realize high band-width, low power con-

sumption and high reliability.

• Extended Data Out Mode operation

FEATURES

• CAS-before-RAS refresh capability

• Part Identification

• RAS-only and Hidden refresh capability

• Fast parallel test mode capability

• TTL(5.0V) compatible inputs and outputs

• Early Write or output enable controlled write

• JEDEC Standard pinout

- KM48C8004C(5.0V, 8K Ref.)

- KM48C8104C(5.0V, 4K Ref.)

• Active Power Dissipation

• Available in Plastic SOJ and TSOP(II) packages

• +5.0V±10% power supply

Unit : mW

Speed

-5

495

440

660

605

-6

• Refresh Cycles

FUNCTIONAL BLOCK DIAGRAM

Part

NO.

Refresh

cycle

Refresh time

Normal

64ms

RAS

CAS

Vcc

Vss

KM48C8004C*

KM48C8104C

Control

Clocks

VBB Generator

* Access mode & RAS only refresh mode

: 8K cycle/64ms

CAS-before-RAS & Hidden refresh mode

: 4K cycle/64ms

Row Decoder

Refresh Timer

Refresh Control

Data in

Buffer

Memory Array

8,388,608 x 8

Cells

DQ0

DQ7

Refresh Counter

Row Address Buffer

Col. Address Buffer

• Performance Range

Speed

Data out

Buffer

tRAC

50ns

60ns

tCAC

13ns

15ns

tRC

tHPC

20ns

25ns

A0~A12

(A0~A11)*1

-5

-6

84ns

104ns

A0~A9

(A0~A10)*1

Column Decoder

Note) *1 : 4K Refresh

SAMSUNG ELECTRONICS CO., LTD. reserves the right to

change products and specifications without notice.

12 3 4 5 6 7...21

中文翻译

下载PDF

与KM48C8104CK-5相关器件

型号	品牌	获取价格	描述	数据表
KM48C8104CK-6	SAMSUNG	获取价格	EDO DRAM, 8MX8, 60ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32
KM48C8104CS-5	SAMSUNG	获取价格	EDO DRAM, 8MX8, 50ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32
KM48C8104CS-6	SAMSUNG	获取价格	EDO DRAM, 8MX8, 60ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32
KM48H8030T-10	SAMSUNG	获取价格	Synchronous DRAM, 8MX8, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66
KM48H8030T-7.5	SAMSUNG	获取价格	Synchronous DRAM, 8MX8, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66
KM48H8030T-8	SAMSUNG	获取价格	Synchronous DRAM, 8MX8, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66
KM48H8031T-10	SAMSUNG	获取价格	Synchronous DRAM, 8MX8, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66
KM48H8031T-7.5	SAMSUNG	获取价格	Synchronous DRAM, 8MX8, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66
KM48H8031T-8	SAMSUNG	获取价格	Synchronous DRAM, 8MX8, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66
KM48L16031BT-F0	SAMSUNG	获取价格	DDR DRAM, 16MX8, 0.8ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, MS-024FC, TSOP2-6

与KM48C8104CK-5相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

4
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

2
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

23
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

24

产品中心

服务支持

精选活动

关于我们

帮助中心

KM48C8104CK-5

KM48C8104CK-5 数据手册

与KM48C8104CK-5相关器件

与KM48C8104CK-5相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

KM48C8104CK-5

KM48C8104CK-5 数据手册

与KM48C8104CK-5相关器件

与KM48C8104CK-5相关文章

您还可以找

您在本页遇到什么问题？