Datasheet > KAD5512HP_09

KAD5512HP_09

更新时间： 2022-12-28 19:50:16

品牌	Logo	应用领域
英特矽尔 - INTERSIL		/
页数	文件大小	规格书
32页	679K
描述
High Performance 12-Bit, 250/210/170/125MSPS ADC

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数据手册

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KAD5512HP_09 数据手册

KAD5512HP

Timing Diagrams

SAMPLE N

INP

INN

CLKN

CLKP

CLKN

CLKP

CPD

LATENCY = L CYCLES

CPD

CLKOUTN

CLKOUTP

CLKOUTN

CLKOUTP

D[10/8/6/4/2/0]P

D[10/8/6/4/2/0]N

N-L

D[11/0]P

D[11/0]N

ODD BITS EVEN BITS ODD BITS EVEN BITS ODD BITS EVEN BITS

EVEN BITS

N-L

N-L + 1

N-L + 2

DATA

N-L

DATA

N-L + 1

FIGURE 1A. DDR

FIGURE 1B. SDR

FIGURE 1. LVDS TIMING DIAGRAMS

SAMPLE N

INP

INN

INP

INN

CLKN

CLKP

CLKN

CLKP

CPD

LATENCY = L CYCLES

CPD

CLKOUT

ODD BITS EVEN BITS ODD BITS EVEN BITS ODD BITS EVEN BITS

EVEN BITS

D[10/8/6/4/2/0]

N-L N-L N-L + 1 N-L + 1 N-L + 2 N-L + 2

DATA

N-L

DATA

D[11/0]

N-L + 1

FIGURE 2A. DDR

FIGURE 2B. SDR

FIGURE 2. CMOS TIMING DIAGRAM

Switching Specifications

PARAMETER

CONDITION

SYMBOL

MIN

TYP

MAX

UNITS

ADC OUTPUT

Aperture Delay

375

RMS Aperture Jitter

Output Clock to Data Propagation Delay, DDR Rising Edge

LVDS Mode

-260

-160

-260

-220

-310

-50

120

230

200

110

200

DDR Falling Edge

(Note 10)

SDR Falling Edge

-40

-10

-90

-50

Output Clock to Data Propagation Delay, DDR Rising Edge

CMOS Mode

DDR Falling Edge

(Note 10)

SDR Falling Edge

FN6808.2

March 4, 2009

1...4 5 678 9 10...32

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