Datasheet > KAD5512HP-12

KAD5512HP-12

更新时间： 2023-12-20 18:44:43

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瑞萨 - RENESAS		/
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34页	1740K
描述
12-Bit, 125MSPS Single-Channel ADC with LVDS/LVCMOS Outputs

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KAD5512HP-12 数据手册

DATASHEET

KAD5512HP

High Performance 12-Bit, 250/210/170/125MSPS ADC

FN6808

Rev 4.00

May 31, 2016

The KAD5512HP is the high performance member of the

KAD5512 family of 12-bit analog-to-digital converters. Designed

with Intersil’s proprietary FemtoCharge™ technology on a

standard CMOS process, the family supports sampling rates of

up to 250MSPS. The KAD5512HP is part of a pin-compatible

portfolio of 10, 12 and 14-bit A/Ds with sample rates ranging

from 125MSPS to 500MSPS.

Features

• Pin-compatible with the KAD5512P Family, offering 2.2dB

higher SNR

• Programmable gain, offset and skew control

• 950MHz analog input bandwidth

• 60fs Clock jitter

A Serial Peripheral Interface (SPI) port allows for extensive

configurability, as well as fine control of various parameters

such as gain and offset.

• Over-range indicator

• Selectable clock divider: ÷1, ÷2 or ÷4

• Clock phase selection

Digital output data is presented in selectable LVDS or CMOS

formats. The KAD5512HP is available in 72 and 48 Ld QFN

packages with an exposed paddle. Operating from a 1.8V

supply, performance is specified across the full industrial

temperature range (-40°C to +85°C).

• Nap and sleep modes

• Two’s complement, gray code or binary data format

• DDR LVDS-compatible or LVCMOS outputs

• Programmable built-in test patterns

• Single-supply 1.8V operation

• Pb-free (RoHS compliant)

Key Specifications

• SNR = 68.2dBFS for f = 105MHz (-1dBFS)

• SFDR = 81.1dBc for f = 105MHz (-1dBFS)

Applications

• Power Consumption

• Power Amplifier linearization

- 429/345mW at 250/125MSPS (SDR Mode)

- 390/309mW at 250/125MSPS (DDR Mode)

• Radar and satellite antenna array processing

• Broadband communications

• High-performance data acquisition

• Communications test equipment

• WiMAX and microwave receivers

CLKP

CLKN

CLKOUTP

CLKOUTN

CLOCK

GENERATION

D[11:0]P

VINP

VINN

12-BIT

250 MSPS

ADC

D[11:0]N

DIGITAL

SHA

ERROR

ORP

CORRECTION

ORN

LVDS/CMOS

OUTFMT

VCM

–

1.25V

DRIVERS

SPI

CONTROL

OUTMODE

FIGURE 1. BLOCK DIAGRAM

FN6808 Rev 4.00

May 31, 2016

Page 1 of 34

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