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KAD5512HP-25Q72 PDF预览

KAD5512HP-25Q72

更新时间： 2024-11-21 20:30:03
品牌 Logo 应用领域
瑞萨 - RENESAS 转换器
页数 文件大小 规格书
34页 1739K
描述
12-Bit, 250MSPS Single-Channel ADC with LVDS/LVCMOS Outputs; QFN48, QFN72; Temp Range: -40° to 85°C

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KAD5512HP-25Q72 技术参数

生命周期：Unknown零件包装代码：QFN, QFN
包装说明：HVQCCN, LCC72,.39SQ,20针数：48, 72
Reach Compliance Code：compliantECCN代码：3A001.A.5.A.3
HTS代码：8542.39.00.01风险等级：5.76
最大模拟输入电压：1.54 V最小模拟输入电压：
最长转换时间：0.004 µs转换器类型：ADC, PROPRIETARY METHOD
JESD-30 代码：S-PQCC-N72JESD-609代码：e4
长度：10 mm最大线性误差 (EL)：0.0488%
湿度敏感等级：3模拟输入通道数量：1
位数：12功能数量：1
端子数量：72最高工作温度：85 °C
最低工作温度：-40 °C输出位码：OFFSET BINARY, 2'S COMPLEMENT BINARY, GRAY CODE
输出格式：PARALLEL, WORD封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装等效代码：LCC72,.39SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：1.8 V
认证状态：Not Qualified采样速率：250 MHz
采样并保持/跟踪并保持：SAMPLE座面最大高度：0.9 mm
子类别：Analog to Digital Converters标称供电电压：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：10 mmBase Number Matches：1

KAD5512HP-25Q72 数据手册

 浏览型号KAD5512HP-25Q72的Datasheet PDF文件第2页浏览型号KAD5512HP-25Q72的Datasheet PDF文件第3页浏览型号KAD5512HP-25Q72的Datasheet PDF文件第4页浏览型号KAD5512HP-25Q72的Datasheet PDF文件第5页浏览型号KAD5512HP-25Q72的Datasheet PDF文件第6页浏览型号KAD5512HP-25Q72的Datasheet PDF文件第7页 
DATASHEET  
KAD5512HP  
High Performance 12-Bit, 250/210/170/125MSPS ADC  
FN6808  
Rev 4.00  
May 31, 2016  
The KAD5512HP is the high performance member of the  
KAD5512 family of 12-bit analog-to-digital converters. Designed  
with Intersil’s proprietary FemtoCharge™ technology on a  
standard CMOS process, the family supports sampling rates of  
up to 250MSPS. The KAD5512HP is part of a pin-compatible  
portfolio of 10, 12 and 14-bit A/Ds with sample rates ranging  
from 125MSPS to 500MSPS.  
Features  
• Pin-compatible with the KAD5512P Family, offering 2.2dB  
higher SNR  
• Programmable gain, offset and skew control  
• 950MHz analog input bandwidth  
• 60fs Clock jitter  
A Serial Peripheral Interface (SPI) port allows for extensive  
configurability, as well as fine control of various parameters  
such as gain and offset.  
• Over-range indicator  
• Selectable clock divider: ÷1, ÷2 or ÷4  
• Clock phase selection  
Digital output data is presented in selectable LVDS or CMOS  
formats. The KAD5512HP is available in 72 and 48 Ld QFN  
packages with an exposed paddle. Operating from a 1.8V  
supply, performance is specified across the full industrial  
temperature range (-40°C to +85°C).  
• Nap and sleep modes  
• Two’s complement, gray code or binary data format  
• DDR LVDS-compatible or LVCMOS outputs  
• Programmable built-in test patterns  
• Single-supply 1.8V operation  
• Pb-free (RoHS compliant)  
Key Specifications  
• SNR = 68.2dBFS for f = 105MHz (-1dBFS)  
IN  
• SFDR = 81.1dBc for f = 105MHz (-1dBFS)  
IN  
Applications  
• Power Consumption  
• Power Amplifier linearization  
- 429/345mW at 250/125MSPS (SDR Mode)  
- 390/309mW at 250/125MSPS (DDR Mode)  
• Radar and satellite antenna array processing  
• Broadband communications  
• High-performance data acquisition  
• Communications test equipment  
• WiMAX and microwave receivers  
CLKP  
CLKN  
CLKOUTP  
CLKOUTN  
CLOCK  
GENERATION  
D[11:0]P  
VINP  
VINN  
12-BIT  
250 MSPS  
ADC  
D[11:0]N  
DIGITAL  
SHA  
ERROR  
ORP  
CORRECTION  
ORN  
LVDS/CMOS  
OUTFMT  
VCM  
+
–
1.25V  
DRIVERS  
SPI  
CONTROL  
OUTMODE  
FIGURE 1. BLOCK DIAGRAM  
FN6808 Rev 4.00  
May 31, 2016  
Page 1 of 34  
1234567...34

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