K7A403609A
K7A401809A
128Kx36 & 256Kx18 Synchronous SRAM
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
1
2
3
4
5
6
7
8
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQPa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
N.C.
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
N.C.
VDD
N.C.
VSS
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQPb
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
N.C.
VDD
ZZ
(20mm x 14mm)
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
K7A401809A(256Kx18)
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A17
Address Inputs
32,33,34,35,36,37,
44,45,46,47,48,49,
50,80,81,82,99,100
83
VDD
VSS
N.C.
Power Supply(+3.3V) 15,41,65,91
Ground
17,40,67,90
No Connect
1,2,3,6,7,14,16,25,28,29,
30,38,39,42,43,51,52,53,
56,57,66,75,78,79,95,96
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx
(x=a,b)
OE
Burst Address Advance
Address Status Processor 84
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
85
89
98
97
92
93,94
DQa0~a7
DQb0~b7
DQPa, Pb
VDDQ
Data Inputs/Outputs
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
Output Power Supply
(2.5V or 3.3V)
4,11,20,27,54,61,70,77
VSSQ
Output Ground
5,10,21,26,55,60,71,76
Output Enable
86
88
87
64
31
GW
BW
ZZ
LBO
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
- 4 -
August 2000
Rev 3.0