Datasheet > K6R1016V1B-JP12

K6R1016V1B-JP12

更新时间： 2023-06-15 00:00:00

品牌	Logo	应用领域
三星 - SAMSUNG		静态存储器光电二极管
页数	文件大小	规格书
9页	207K
描述
Standard SRAM, 64KX16, 12ns, CMOS, PDSO44, PLASTIC, SOJ-44

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数据手册

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K6R1016V1B-JP12 数据手册

PRELIMINARY

Preliminary

PRELIMINARY

CMOS SRAM

K6R1016V1B-C/B-L, K6R1016V1B-I/B-P

64K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating)

FEATURES

• Fast Access Time 8,10,12ns(Max.)

• Low Power Dissipation

Standby (TTL) : 50mA(Max.)

(CMOS): 5mA(Max.)

GENERAL DESCRIPTION

The K6R1016V1B is a 1,048,576-bit high-speed Static Random

Access Memory organized as 65,536 words by 16 bits. The

K6R1016V1B uses 16 common input and output lines and has

an output enable pin which operates faster than address

access time at read cycle. Also it allows that lower and upper

byte access by data byte control (UB, LB). The device is fabri-

cated using SAMSUNG¢s advanced CMOS process and

designed for high-speed circuit technology. It is particularly well

suited for use in high-density high-speed system applications.

The K6R1016V1B is packaged in a 400mil 44-pin plastic SOJ

or TSOP2 forward.

0.7mA(Max.) L-Ver. only

Operating K6R1016V1B-8 : 200mA(Max.)

K6R1016V1B-10: 195mA(Max.)

K6R1016V1B-12: 190mA(Max.)

• Single 3.3±0.3V Power Supply

• TTL Compatible Inputs and Outputs

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• 2V Minimum Data Retention; L-Ver. only

• Center Power/Ground Pin Configuration

• Data Byte Control: LB: I/O1~ I/O8, UB: I/O9~ I/O16

• Standard Pin Configuration

PIN CONFIGURATION (Top View)

44 A15

43 A14

42 A13

41 OE

K6R1016V1B-J: 44-SOJ-400

K6R1016V1B-T: 44-TSOP2-400BF

40 UB

I/O1

I/O2

I/O3

39 LB

ORDERING INFORMATION

38 I/O16

37 I/O15

36 I/O14

35 I/O13

34 Vss

33 Vcc

32 I/O12

31 I/O11

30 I/O10

29 I/O9

28 N.C

27 A12

26 A11

25 A10

24 A9

K6R1016V1B-C8/C10/C12

Commercial Temp.

K6R1016V1B-I8/I10/I12

Industrial Temp.

I/O4 10

Vcc 11

Vss 12

I/O5 13

I/O6 14

I/O7 15

I/O8 16

WE 17

A5 18

SOJ/

TSOP2

FUNCTIONAL BLOCK DIAGRAM

Clk Gen.

Pre-Charge Circuit

A6 19

Memory Array

256 Rows

256x16 Columns

A7 20

A8 21

N.C 22

23 N.C

PIN FUNCTION

Data

Cont.

I/O Circuit &

I/O1~I/O8

Column Select

Pin Name

A0 - A15

Pin Function

Data

Cont.

Address Inputs

Write Enable

Chip Select

I/O9~I/O16

Gen.

CLK

A8 A9 A10 A11A12 A13 A14 A15

Output Enable

Lower-byte Control(I/O1~I/O8)

Upper-byte Control(I/O9~I/O16)

Data Inputs/Outputs

Power(+3.3V)

I/O1 ~ I/O16

VCC

VSS

Ground

N.C

No Connection

Rev 2.1

August 1998

- 2 -

123 4 5 6 7...9

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与K6R1016V1B-JP12相关器件

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K6R1016V1B-TL10	SAMSUNG	Standard SRAM, 64KX16, 10ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44	获取价格
K6R1016V1B-TL12	SAMSUNG	Standard SRAM, 64KX16, 12ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44	获取价格
K6R1016V1B-TP10	SAMSUNG	Standard SRAM, 64KX16, 10ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44	获取价格
K6R1016V1B-TP10T	SAMSUNG	Standard SRAM, 64KX16, 10ns, CMOS, PDSO44	获取价格
K6R1016V1B-TP12	SAMSUNG	Standard SRAM, 64KX16, 12ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44	获取价格
K6R1016V1C	SAMSUNG	64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating) Operated at Commercial and Industria	获取价格