Datasheet > K4S56323PF-FF900

K4S56323PF-FF900

更新时间： 2023-01-15 00:00:00

品牌	Logo	应用领域
三星 - SAMSUNG		动态存储器
页数	文件大小	规格书
12页	143K
描述
Synchronous DRAM, 8MX32, 7ns, CMOS, PBGA90, FBGA-90

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K4S56323PF-FF900 数据手册

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K4S56323PF-F(H)G/F

Mobile-SDRAM

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Parameter

Symbol

Unit

Note

-75

-90

-1L

Row active to row active delay

RAS to CAS delay

tRRD(min)

tRCD(min)

tRP(min)

22.5

Row precharge time

tRAS(min)

tRAS(max)

tRC(min)

Row active time

100

Row cycle time

72.5

Last data in to row precharge

Last data in to Active delay

Last data in to new col. address delay

Last data in to burst stop

tRDL(min)

tDAL(min)

tCDL(min)

tBDL(min)

tARFC(min)

tSRFX(min)

tCCD(min)

tRDL + tRP

CLK

Auto refresh cycle time

120

Exit self refresh to active command

Col. address to col. address delay

CLK

Number of valid output data

CAS latency=3

CAS latency=2

CAS latency=1

NOTES:

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next

higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

September 2004

1...4 5 678 9 10...12

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