Datasheet > K4S561632D-NC60

K4S561632D-NC60

更新时间： 2023-01-03 09:47:27

品牌	Logo	应用领域
三星 - SAMSUNG		动态存储器光电二极管
页数	文件大小	规格书
9页	46K
描述
Synchronous DRAM, 16MX16, 5ns, CMOS, PDSO54, 0.300 X 0.551 INCH, 0.50 MM PITCH, STSOP2-54

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K4S561632D-NC60 数据手册

K4S561632D

CMOS SDRAM

PIN CONFIGURATION (Top view)

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

VSS

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

VDD

LDQM

54 PIN sTSOP(II)

300mil x 551mil

(7.62mm x 14.00mm)

(0.5 mm PIN PITCH)

Bank Address

BA0-BA1

UDQM

CLK

CKE

A12

RowAddress

A0-A12

CAS

RAS

Auto Precharge

A10

A11

BA0

BA1

AP/A10

VSS

VDD

PIN FUNCTION DESCRIPTION

Name

System cock

Input Function

Active on the positive going edge to sample all inputs.

CLK

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Chip select

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

CKE

Clock enable

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA12, Column address : CA 0 ~ CA8

A0 ~ A12

BA0 ~ BA1

RAS

Address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Bank select address

Row address strobe

Column address strobe

Write enable

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

CAS

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when L(U)DQM active.

L(U)DQM

Data input/output mask

DQ0 ~ 15

VDD/VSS

Data input/output

Data inputs/outputs are multiplexed on the same pins.

Power and ground for the input buffers and the core logic.

Power supply/ground

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

VDDQ/VSSQ

Data output power/ground

No connection

/reserved for future use

N.C/RFU

This pin is recommended to be left No Connection on the device.

Rev. 0.1 Aug. 2002

1 2 345 6 7...9

中文翻译

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与K4S561632D-NC60相关器件

型号	品牌	获取价格	描述	数据表
K4S561632D-NC600	SAMSUNG	获取价格	Synchronous DRAM, 16MX16, 5ns, CMOS, PDSO54, STSOP2-54
K4S561632D-NC75	SAMSUNG	获取价格	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.300 X 0.551 INCH, 0.50 MM PITCH, STSOP2-5
K4S561632D-NC7C0	SAMSUNG	获取价格	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, STSOP2-54
K4S561632D-NL1H	SAMSUNG	获取价格	Synchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, 0.300 X 0.551 INCH, 0.50 MM PITCH, STSOP2-54
K4S561632D-NL1H0	SAMSUNG	获取价格	Synchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, STSOP2-54
K4S561632D-NL1L	SAMSUNG	获取价格	Synchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, 0.300 X 0.551 INCH, 0.50 MM PITCH, STSOP2-54
K4S561632D-NL1L0	SAMSUNG	获取价格	Synchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, STSOP2-54
K4S561632D-NL60	SAMSUNG	获取价格	Synchronous DRAM, 16MX16, 5ns, CMOS, PDSO54, 0.300 X 0.551 INCH, 0.50 MM PITCH, STSOP2-54
K4S561632D-NL600	SAMSUNG	获取价格	Synchronous DRAM, 16MX16, 5ns, CMOS, PDSO54, STSOP2-54
K4S561632D-NL75	SAMSUNG	获取价格	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.300 X 0.551 INCH, 0.50 MM PITCH, STSOP2-5

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