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K4M64163LK-BG1L0 PDF预览

K4M64163LK-BG1L0

更新时间: 2023-08-15 00:00:00
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器
页数 文件大小 规格书
12页 113K
描述
Synchronous DRAM, 4MX16, 7ns, CMOS, PBGA54, LEAD FREE, FBGA-54

K4M64163LK-BG1L0 数据手册

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K4M64163LK - R(B)N/G/L/F  
Mobile-SDRAM  
AC CHARACTERISTICS(AC operating conditions unless otherwise noted)  
-75  
-1H  
-1L  
Parameter  
Symbol  
Unit Note  
Min  
7.5  
9.0  
-
Max  
Min  
9.0  
9.0  
-
Max  
Min  
9.0  
12  
Max  
CLK cycle time  
CLK cycle time  
CLK cycle time  
CAS latency=3  
CAS latency=2  
CAS latency=1  
CAS latency=3  
CAS latency=2  
CAS latency=1  
CAS latency=3  
CAS latency=2  
CAS latency=1  
t
t
t
CC  
CC  
CC  
1000  
1000  
1000  
ns  
ns  
ns  
1
1,2  
2
25  
CLK to valid output delay  
CLK to valid output delay  
CLK to valid output delay  
Output data hold time  
Output data hold time  
Output data hold time  
CLK high pulse width  
CLK low pulse width  
Input setup time  
t
t
t
SAC  
SAC  
SAC  
5.4  
7
7
7
-
7
8
-
20  
t
OH  
OH  
OH  
2.5  
2.5  
-
2.5  
2.5  
-
2.5  
2.5  
2.5  
3.0  
3.0  
2.5  
1.0  
1
t
t
t
CH  
CL  
SS  
SH  
SLZ  
2.5  
2.5  
2.0  
1.0  
1
3.0  
3.0  
2.5  
1.0  
1
ns  
ns  
ns  
ns  
ns  
3
3
3
3
2
t
t
Input hold time  
t
CLK to output in Low-Z  
t
CAS latency=3  
CAS latency=2  
CAS latency=1  
5.4  
7
7
7
-
7
8
CLK to output in Hi-Z  
t
SHZ  
ns  
-
20  
NOTES :  
1. Parameters depend on programmed CAS latency.  
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.  
3. Assumed input rise and fall time (tr & tf) = 1ns.  
If tr & tf is longer than 1ns, transient time compensation should be considered,  
i.e., [(tr + tf)/2-1]ns should be added to the parameter.  
8
January 2006  

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