Datasheet > K4M64163LK-BG1L0

K4M64163LK-BG1L0

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
三星 - SAMSUNG		动态存储器
页数	文件大小	规格书
12页	113K
描述
Synchronous DRAM, 4MX16, 7ns, CMOS, PBGA54, LEAD FREE, FBGA-54

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K4M64163LK-BG1L0 数据手册

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K4M64163LK - R(B)N/G/L/F

Mobile-SDRAM

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Parameter

Symbol

Unit

Note

-75

-1H

-1L

Row active to row active delay

RAS to CAS delay

RRD(min)

RCD(min)

Row precharge time

RP(min)

RAS(min)

RAS(max)

RC(min)

RDL(min)

DAL(min)

CDL(min)

BDL(min)

CCD(min)

Row active time

100

Row cycle time

1, 6

Last data in to row precharge

Last data in to Active delay

Last data in to new col. address delay

Last data in to burst stop

CLK

tRDL + tRP

CLK

Col. address to col. address delay

Number of valid output data

CAS latency=3

CAS latency=2

CAS latency=1

NOTES:

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and precharge command(tRP).

4. All parts allow every cycle column address change.

5. In case of row precharge interrupt, auto precharge and read burst stop.

6. Maximum burst refresh cycle : 8

January 2006

1...4 5 678 9 10...12

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