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K4M641633K-BG1LT PDF预览

K4M641633K-BG1LT

更新时间: 2024-01-08 09:24:40
品牌 Logo 应用领域
三星 - SAMSUNG 时钟动态存储器内存集成电路
页数 文件大小 规格书
12页 113K
描述
Synchronous DRAM, 4MX16, 7ns, CMOS, PBGA54

K4M641633K-BG1LT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:FBGA, BGA54,9X9,32
Reach Compliance Code:compliant风险等级:5.84
最长访问时间:7 ns最大时钟频率 (fCLK):111 MHz
I/O 类型:COMMON交错的突发长度:1,2,4,8
JESD-30 代码:S-PBGA-B54JESD-609代码:e3
内存密度:67108864 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:16湿度敏感等级:1
端子数量:54字数:4194304 words
字数代码:4000000最高工作温度:85 °C
最低工作温度:-25 °C组织:4MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:FBGA封装等效代码:BGA54,9X9,32
封装形状:SQUARE封装形式:GRID ARRAY, FINE PITCH
峰值回流温度(摄氏度):225电源:3/3.3 V
认证状态:Not Qualified刷新周期:4096
连续突发长度:1,2,4,8,FP最大待机电流:0.0005 A
子类别:DRAMs最大压摆率:0.1 mA
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:MATTE TIN
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED

K4M641633K-BG1LT 数据手册

 浏览型号K4M641633K-BG1LT的Datasheet PDF文件第4页浏览型号K4M641633K-BG1LT的Datasheet PDF文件第5页浏览型号K4M641633K-BG1LT的Datasheet PDF文件第6页浏览型号K4M641633K-BG1LT的Datasheet PDF文件第8页浏览型号K4M641633K-BG1LT的Datasheet PDF文件第9页浏览型号K4M641633K-BG1LT的Datasheet PDF文件第10页 
K4M641633K - R(B)N/G/L/F  
Mobile-SDRAM  
OPERATING AC PARAMETER  
(AC operating conditions unless otherwise noted)  
Version  
Parameter  
Symbol  
Unit  
Note  
-75  
15  
18  
18  
45  
-1H  
-1L  
18  
24  
24  
60  
Row active to row active delay  
RAS to CAS delay  
t
t
RRD(min)  
RCD(min)  
18  
ns  
ns  
1
1
1
1
18  
Row precharge time  
t
RP(min)  
RAS(min)  
RAS(max)  
RC(min)  
RDL(min)  
DAL(min)  
CDL(min)  
BDL(min)  
CCD(min)  
18  
ns  
t
50  
ns  
Row active time  
t
100  
us  
Row cycle time  
t
63  
68  
84  
ns  
1,6  
2
Last data in to row precharge  
Last data in to Active delay  
Last data in to new col. address delay  
Last data in to burst stop  
t
2
CLK  
-
t
tRDL + tRP  
3
t
1
1
1
2
1
0
CLK  
CLK  
CLK  
2
t
2
Col. address to col. address delay  
Number of valid output data  
Number of valid output data  
Number of valid output data  
t
4
CAS latency=3  
CAS latency=2  
CAS latency=1  
ea  
5
NOTES:  
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time  
and then rounding off to the next higher integer.  
2. Minimum delay is required to complete write.  
3. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and precharge command(tRP).  
4. All parts allow every cycle column address change.  
5. In case of row precharge interrupt, auto precharge and read burst stop.  
6. Maximum burst refresh cycle : 8  
7
January 2006  

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