K4E660811D,K4E640811D
CMOS DRAM
8M x 8bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 8,388,608 x 8 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-50 or -60), package type (SOJ or TSOP-
II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities.
This 8Mx8 EDO Mode DRAM family is fabricated using Samsung¢s advanced CMOS process to realize high band-width, low power con-
sumption and high reliability.
FEATURES
• Extended Data Out Mode operation
• Part Identification
- K4E660811D-JC(5.0V, 8K Ref., SOJ)
- K4E640811D-JC(5.0V, 4K Ref., SOJ)
- K4E660811D-TC(5.0V, 8K Ref., TSOP)
- K4E640811D-TC(5.0V, 4K Ref., TSOP)
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Fast parallel test mode capability
• TTL(5.0V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Active Power Dissipation
• Available in Plastic SOJ and TSOP(II) packages
• +5.0V±10% power supply
Unit : mW
4K
Speed
-50
8K
495
440
660
605
-60
• Refresh Cycles
FUNCTIONAL BLOCK DIAGRAM
Part
NO.
Refresh
cycle
Refresh time
Normal
RAS
CAS
W
Vcc
Vss
K4E660811D*
K4E640811D
8K
4K
64ms
Control
Clocks
VBB Generator
* Access mode & RAS only refresh mode
: 8K cycle/64ms
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms
Row Decoder
Refresh Timer
Refresh Control
Data in
Buffer
Memory Array
8,388,608 x 8
Cells
DQ0
to
DQ7
Refresh Counter
Row Address Buffer
Col. Address Buffer
• Performance Range
Speed
Data out
Buffer
tRAC
50ns
60ns
tCAC
13ns
15ns
tRC
tHPC
20ns
25ns
A0~A12
(A0~A11)*1
OE
-50
-60
84ns
104ns
A0~A9
(A0~A10)*1
Column Decoder
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.